Skip to content
GitLab
Explore
Sign in
Projects
AIDA-2020 TLU
Repository
fmc-mtlu
firmware
hdl
common
logic_clocks_rtl.vhd
Find file
Blame
History
Permalink
Added more registers to try to improve timing. Still get timing errors
· cd6d32d4
David Cussans
authored
Sep 03, 2015
cd6d32d4