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AIDA-2020 TLU - Software
Commit e5d82fc9 authored by Paolo Baesso's avatar Paolo Baesso
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Minor change in Si5345 to add verbose functionality during configuratioN

parent 816f2e27
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Showing with 5 additions and 3 deletions
packages/si5345.py
View file @ e5d82fc9
...@@ -87,7 +87,7 @@ class si5345: ...@@ -87,7 +87,7 @@ class si5345:
self.i2c.write( self.slaveaddr, myaddr, mystop) self.i2c.write( self.slaveaddr, myaddr, mystop)
#time.sleep(0.1) #time.sleep(0.1)
res= self.i2c.read( self.slaveaddr, nwords) res= self.i2c.read( self.slaveaddr, nwords)
print " Si5345 EPROM: " print " Si5345 EEPROM: "
result="\t" result="\t"
for iaddr in reversed(res): for iaddr in reversed(res):
result+="%#02x "%(iaddr) result+="%#02x "%(iaddr)
...@@ -119,7 +119,7 @@ class si5345: ...@@ -119,7 +119,7 @@ class si5345:
print "\t ", len(regSettingList), "elements" print "\t ", len(regSettingList), "elements"
return regSettingList return regSettingList
def writeConfiguration(self, regSettingList): def writeConfiguration(self, regSettingList, verbose= 0):
print " Si5345 Writing configuration:" print " Si5345 Writing configuration:"
#regSettingList= list(regSettingCsv) #regSettingList= list(regSettingCsv)
counter=0 counter=0
...@@ -127,9 +127,11 @@ class si5345: ...@@ -127,9 +127,11 @@ class si5345:
regAddr= int(item[0], 16) regAddr= int(item[0], 16)
regData=[0] regData=[0]
regData[0]= int(item[1], 16) regData[0]= int(item[1], 16)
print "\t", counter, "Reg:", hex(regAddr), "Data:", regData if verbose:
print "\t", counter, "Reg:", hex(regAddr), "Data:", regData
counter += 1 counter += 1
self.writeRegister(regAddr, regData, False) self.writeRegister(regAddr, regData, False)
print "\tSi5345 configuration done"
def checkDesignID(self): def checkDesignID(self):
regAddr= 0x026B regAddr= 0x026B
......
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