Dummy_DUT now works. The fifo is still work in progress but the extended BUSY…

Dummy_DUT now works. The fifo is still work in progress but the extended BUSY line seems to work fine. Currently DUT 1 and 2 have extended BUSY (about 800 us) while 3 and 4 have normal BUSY

Dummy_DUT now works. The fifo is still work in progress but the extended BUSY…
Dummy_DUT now works. The fifo is still work in progress but the extended BUSY line seems to work fine. Currently DUT 1 and 2 have extended BUSY (about 800 us) while 3 and 4 have normal BUSY
d6b87ff6 · Paolo Baesso · d6c5df5f · d6b87ff6
Commit d6b87ff6 authored Nov 22, 2017 by Paolo Baesso
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Dummy_DUT.vhd EUDETdummy/hdl/Dummy_DUT.vhd +1 -1

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--- a/EUDETdummy/hdl/Dummy_DUT.vhd
+++ b/EUDETdummy/hdl/Dummy_DUT.vhd
@@ -83,7 +83,7 @@ architecture RTL of Dummy_DUT is

  signal DUTClockCounter : unsigned(4 downto 0) := ( others => '0');
  
-  signal s_busySR : unsigned( 15 downto 0) := ( others => '0' );  -- --! Shift register to generate stretch
+  signal s_busySR : unsigned( 14 downto 0) := ( others => '0' );  -- --! Shift register to generate stretch

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