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AIDA-2020 TLU - Software
Commit cac053fd authored by Paolo Baesso's avatar Paolo Baesso
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Extend BUSY signal by 6.4 us. Dummy FIFO still bugged.

parent 493db402
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Showing with 66 additions and 43 deletions
EUDETdummy/hdl/Dummy_DUT.vhd
View file @ cac053fd
......@@ -69,7 +69,7 @@ architecture RTL of Dummy_DUT is
--incoming
--trigger number
type state_type is (IDLE , WAIT_FOR_TRIGGER_LOW , CLOCKING , OUTPUT_TRIGGER_NUMBER);
type state_type is (IDLE , WAIT_FOR_TRIGGER_LOW , CLOCKING , OUTPUT_TRIGGER_NUMBER, BUSYDELAY);
signal state : state_type := IDLE;
signal next_state : state_type := IDLE;
......@@ -83,7 +83,7 @@ architecture RTL of Dummy_DUT is
signal DUTClockCounter : unsigned(4 downto 0) := ( others => '0');
signal s_busySR : unsigned( 7 downto 0) := ( others => '0' ); -- --! Shift register to generate stretch
signal s_busySR : unsigned( 10 downto 0) := ( others => '0' ); -- --! Shift register to generate stretch
begin
......@@ -104,40 +104,40 @@ begin
output => Registered_RST);
-- busy_control: process (clk , state)
-- begin -- process busy_control
-- if rising_edge(clk) then
-- if state = IDLE then
-- busy <= '0';
-- else
-- busy <= '1';
-- end if;
-- end if;
-- end process busy_control;
busy_control: process (clk , state)
begin -- process busy_control
if rising_edge(clk) then
if (stretchBusy ='1') then
if ((state = IDLE) and (s_busySR=0)) then
busy <= '0';
s_busySR <= ( others => '1' );
elsif ( (state = IDLE) and (s_busySR /= 0) ) then
busy <= '1';
s_busySR <= s_busySR -1;
else
busy <= '1';
s_busySR <= s_busySR -1;
end if;
else
if state = IDLE then
busy <= '0';
else
busy <= '1';
end if;
end if;
begin -- process busy_control
if rising_edge(clk) then
if state = IDLE then
busy <= '0';
else
busy <= '1';
end if;
end process busy_control;
end if;
end process busy_control;
-- busy_control: process (clk , state)
-- begin -- process busy_control
-- if rising_edge(clk) then
-- if (stretchBusy ='1') then
-- if ((state = IDLE) and (s_busySR=0)) then
-- busy <= '0';
-- s_busySR <= ( others => '1' );
-- elsif ( (state = IDLE) and (s_busySR /= 0) ) then
-- busy <= '1';
-- s_busySR <= s_busySR -1;
-- else
-- busy <= '1';
-- s_busySR <= s_busySR -1;
-- end if;
-- else
-- if state = IDLE then
-- busy <= '0';
-- else
-- busy <= '1';
-- end if;
-- end if;
-- end if;
-- end process busy_control;
clock_control: process (clk , state , TriggerBitCounter )
begin -- process busy_control
......@@ -201,11 +201,22 @@ begin
end if;
end process strobe_control;
busy_delay_control: process(clk, state)
begin
if rising_edge(clk) then
if state= BUSYDELAY then
s_busySR <= s_busySR -1;
elsif state= WAIT_FOR_TRIGGER_LOW then
s_busySR <= ( others => '1' );
end if;
end if;
end process busy_delay_control;
--! @brief controls the next state in the state machine
-- type : combinational
-- inputs : pattern_we, mask_we , beam_state_counter
-- outputs: state , beam_state_counter
state_logic: process (state, TriggerBitCounter , registered_trigger ,InternalDUTClk )
state_logic: process (state, TriggerBitCounter , registered_trigger ,InternalDUTClk, stretchBusy, s_busySR )
begin -- process state_logic
case state is
......@@ -214,7 +225,7 @@ begin
next_state <= WAIT_FOR_TRIGGER_LOW;
else
next_state <= IDLE;
end if;
end if;
when WAIT_FOR_TRIGGER_LOW =>
if ( registered_trigger = '0' ) then
......@@ -231,7 +242,18 @@ begin
end if;
when OUTPUT_TRIGGER_NUMBER =>
next_state <= IDLE;
if (stretchBusy ='1') then
next_state <= BUSYDELAY;
else
next_state <= IDLE;
end if;
when BUSYDELAY =>
if (s_busySR /= 0) then
next_state <= BUSYDELAY;
else
next_state <= IDLE;
end if;
when others =>
next_state <= IDLE;
......
EUDETdummy/hdl/top_EUDET_dummy.vhd
View file @ cac053fd
......@@ -23,7 +23,7 @@ use work.ipbus.ALL;
entity top_EUDET_dummy is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"ffff0003"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"ffff0005"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......@@ -504,6 +504,7 @@ begin
)
PORT MAP (
clk_4x_logic_i => clk_4x_logic,
--clk_4x_logic_i => sysclk_40,
data_strobe_i => TriggerNumberStrobe(0),
event_data_i => TrigNArray(0),
ipbus_clk_i => clk_ipb,
......
EUDETdummy/scripts/startEUDETdummy.py
View file @ cac053fd
......@@ -66,11 +66,11 @@ if __name__ == "__main__":
logdata= True
EUDummy.start(logdata)
time.sleep(0.2)
#nwords= int( EUDummy.getFifoLevel() )
#print nwords
#myarray= EUDummy.getFifoData(nwords)
#for iel in myarray:
# print iel >> 16
nwords= int( EUDummy.getFifoLevel() )
print nwords
myarray= EUDummy.getFifoData(nwords)
for iel in myarray:
print iel >> 16
EUDummy.stop()
# prompt = MyPrompt()
......
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