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AIDA-2020 TLU - Software
Commits
4ab568da
Commit
4ab568da
authored
Nov 16, 2017
by
Paolo Baesso
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6 changed files
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309 additions
and
214 deletions
+309
-214
EUDET_dummy_constr.xdc
EUDETdummy/constraints/EUDET_dummy_constr.xdc
+33
-1
Dummy_DUT.vhd
EUDETdummy/hdl/Dummy_DUT.vhd
+38
-11
dummyEventBuffer_rtl.vhd
EUDETdummy/hdl/dummyEventBuffer_rtl.vhd
+168
-0
top_EUDET_dummy.vhd
EUDETdummy/hdl/top_EUDET_dummy.vhd
+62
-200
EUDETdummyaddrmap.xml
EUDETdummy/scripts/EUDETdummyaddrmap.xml
+2
-2
startEUDETdummy.py
EUDETdummy/scripts/startEUDETdummy.py
+6
-0
No files found.
EUDETdummy/constraints/EUDET_dummy_constr.xdc
View file @
4ab568da
...
...
@@ -28,8 +28,8 @@ set_property PACKAGE_PIN F6 [get_ports gpio]
## Crystal clock
set_property IOSTANDARD LVDS_25 [get_ports sysclk_40_i_p]
set_property PACKAGE_PIN T4 [get_ports sysclk_40_i_n]
set_property PACKAGE_PIN T5 [get_ports sysclk_40_i_p]
set_property PACKAGE_PIN T4 [get_ports sysclk_40_i_n]
## Output clock (currently not working so set to 0)
set_property IOSTANDARD LVCMOS33 [get_ports sysclk_50_o_p]
...
...
@@ -106,3 +106,35 @@ set_property PACKAGE_PIN G3 [get_ports {dut_clk_i[3]}]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list sysclk_40_BUFG]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {TrigNArray[0][0]} {TrigNArray[0][1]} {TrigNArray[0][2]} {TrigNArray[0][3]} {TrigNArray[0][4]} {TrigNArray[0][5]} {TrigNArray[0][6]} {TrigNArray[0][7]} {TrigNArray[0][8]} {TrigNArray[0][9]} {TrigNArray[0][10]} {TrigNArray[0][11]} {TrigNArray[0][12]} {TrigNArray[0][13]} {TrigNArray[0][14]} {TrigNArray[0][15]} {TrigNArray[0][16]} {TrigNArray[0][17]} {TrigNArray[0][18]} {TrigNArray[0][19]} {TrigNArray[0][20]} {TrigNArray[0][21]} {TrigNArray[0][22]} {TrigNArray[0][23]} {TrigNArray[0][24]} {TrigNArray[0][25]} {TrigNArray[0][26]} {TrigNArray[0][27]} {TrigNArray[0][28]} {TrigNArray[0][29]} {TrigNArray[0][30]} {TrigNArray[0][31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {busy_o_OBUF[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {dut_clk_o_OBUF[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list TriggerNumberStrobe6_out]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets sysclk_40_BUFG]
EUDETdummy/hdl/Dummy_DUT.vhd
View file @
4ab568da
...
...
@@ -39,9 +39,10 @@ entity Dummy_DUT is
CLK
:
in
STD_LOGIC
;
--! this is the USB clock.
RST
:
in
STD_LOGIC
;
--! Synchronous clock
Trigger
:
in
STD_LOGIC
;
--! Trigger from TLU
stretchBusy
:
in
STD_LOGIC
;
-- flag: if 1, then we want to extend the BUSY signal
Busy
:
out
STD_LOGIC
;
--! Busy to TLU
DUTClk
:
out
STD_LOGIC
;
--! clock from DUT
TriggerNumber
:
out
STD_LOGIC_VECTOR
(
15
downto
0
);
TriggerNumber
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
TriggerNumberStrobe
:
out
STD_LOGIC
;
FSM_Error
:
out
STD_LOGIC
);
...
...
@@ -63,7 +64,7 @@ architecture RTL of Dummy_DUT is
signal
Registered_Trigger
,
Registered_RST
:
std_logic
;
-- trigger and reset signals after being registered to suppress meta-stability.
signal
TriggerShiftRegister
:
STD_LOGIC_VECTOR
(
15
downto
0
);
--! register
signal
TriggerShiftRegister
:
STD_LOGIC_VECTOR
(
31
downto
0
);
--! register
--to accept
--incoming
--trigger number
...
...
@@ -81,6 +82,8 @@ architecture RTL of Dummy_DUT is
constant
TriggerBitCounterLimit
:
unsigned
(
4
downto
0
)
:
=
to_unsigned
(
16
,
5
);
signal
DUTClockCounter
:
unsigned
(
4
downto
0
)
:
=
(
others
=>
'0'
);
signal
s_busySR
:
unsigned
(
15
downto
0
)
:
=
(
others
=>
'0'
);
-- --! Shift register to generate stretch
begin
...
...
@@ -101,16 +104,40 @@ begin
output
=>
Registered_RST
);
-- busy_control: process (clk , state)
-- begin -- process busy_control
-- if rising_edge(clk) then
-- if state = IDLE then
-- busy <= '0';
-- else
-- busy <= '1';
-- end if;
-- end if;
-- end process busy_control;
busy_control
:
process
(
clk
,
state
)
begin
-- process busy_control
if
rising_edge
(
clk
)
then
if
state
=
IDLE
then
busy
<=
'0'
;
else
busy
<=
'1'
;
begin
-- process busy_control
if
rising_edge
(
clk
)
then
if
(
stretchBusy
=
'1'
)
then
if
((
state
=
IDLE
)
and
(
s_busySR
=
0
))
then
busy
<=
'0'
;
s_busySR
<=
(
others
=>
'1'
);
elsif
(
(
state
=
IDLE
)
and
(
s_busySR
/=
0
)
)
then
busy
<=
'1'
;
s_busySR
<=
s_busySR
-1
;
else
busy
<=
'1'
;
s_busySR
<=
s_busySR
-1
;
end
if
;
else
if
state
=
IDLE
then
busy
<=
'0'
;
else
busy
<=
'1'
;
end
if
;
end
if
;
end
if
;
end
if
;
end
process
busy_control
;
end
process
busy_control
;
clock_control
:
process
(
clk
,
state
,
TriggerBitCounter
)
begin
-- process busy_control
...
...
@@ -153,7 +180,7 @@ begin
elsif
state
=
CLOCKING
then
if
(
InternalDUTClk
=
'1'
)
and
(
DUTClockCounter
=
to_unsigned
(
1
,
4
))
then
-- if (InternalDUTClk = '1') and (DUTClockCounter=to_unsigned(1,DUTClockCounter'length )) then
TriggerShiftRegister
<=
trigger
&
TriggerShiftRegister
(
15
downto
1
)
;
TriggerShiftRegister
<=
trigger
&
TriggerShiftRegister
(
31
downto
1
)
;
-- TriggerShiftRegister <= trigger & TriggerShiftRegister( TriggerShiftRegister'high downto 1) ;
else
TriggerShiftRegister
<=
TriggerShiftRegister
;
...
...
EUDETdummy/hdl/dummyEventBuffer_rtl.vhd
0 → 100644
View file @
4ab568da
--=============================================================================
--! @file eventBuffer_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.eventBuffer.rtl
--
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY
ieee
;
USE
ieee
.
std_logic_1164
.
all
;
USE
ieee
.
numeric_std
.
all
;
USE
work
.
ipbus
.
all
;
--! @brief Stores input words (64bits) for readout over IPBus.
--! Uses a FIFO ( 64bits at input, 32 bits at output )
--
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:24:50 11/13/12
--
--! @version v0.1
--
--! @details
--! \n\nIPBus Address map:
--! \li 0x0000 - FIFO data
--! \li 0x0001 - FIFO fill level
--! \li 0x0010 - FIFO status/control: (Writing Bit-0 resets pointers, Reading bit-1 returns "prog_full" flag)
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--------------------------------------------------------------------------------
ENTITY
eventBuffer
IS
GENERIC
(
g_EVENT_DATA_WIDTH
:
positive
:
=
32
;
g_IPBUS_WIDTH
:
positive
:
=
32
;
g_READ_COUNTER_WIDTH
:
positive
:
=
13
);
PORT
(
clk_4x_logic_i
:
IN
std_logic
;
data_strobe_i
:
IN
std_logic
;
-- Indicates data to transfer
event_data_i
:
IN
std_logic_vector
(
g_EVENT_DATA_WIDTH
-1
DOWNTO
0
);
ipbus_clk_i
:
IN
std_logic
;
ipbus_i
:
IN
ipb_wbus
;
ipbus_reset_i
:
IN
std_logic
;
strobe_4x_logic_i
:
IN
std_logic
;
--trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
rst_fifo_o
:
OUT
std_logic
;
--! rst signal to first level fifos
buffer_full_o
:
OUT
std_logic
;
--! Goes high when event buffer almost full
ipbus_o
:
OUT
ipb_rbus
;
logic_reset_i
:
IN
std_logic
-- reset buffers when high. Synch withclk_4x_logic
);
-- Declarations
END
ENTITY
eventBuffer
;
--
ARCHITECTURE
rtl
OF
eventBuffer
IS
signal
s_rd_data_count
:
std_logic_vector
(
g_READ_COUNTER_WIDTH
-1
downto
0
)
:
=
(
others
=>
'0'
);
signal
s_fifo_fill_level
:
std_logic_vector
(
g_IPBUS_WIDTH
-1
downto
0
)
:
=
(
others
=>
'0'
);
-- read-counter - 2*write_count
signal
s_write_strobe
:
std_logic
:
=
'0'
;
signal
s_rst_fifo
,
s_rst_fifo_ipb
:
std_logic
:
=
'0'
;
-- ! Take high to reset FIFO pointers.
signal
s_fifo_prog_full
:
std_logic
:
=
'0'
;
-- ! Controlled by programmable-full flag of FIFO core
signal
s_fifo_rd_en
:
std_logic
:
=
'0'
;
-- ! Take high to clock data out of FIFO
signal
s_fifo_dout
:
std_logic_vector
(
g_IPBUS_WIDTH
-1
downto
0
);
-- ! Output from FIFO ( fall-through mode)
signal
s_fifo_valid
:
std_logic
:
=
'1'
;
-- ! High when data in FIFO
signal
s_fifo_full
,
s_fifo_almost_full
,
s_fifo_empty
,
s_fifo_almost_empty
:
std_logic
:
=
'0'
;
-- ! full and empty FIFO flags
signal
s_fifo_status_ipb
,
s_fifo_fill_level_d1
:
std_logic_vector
(
ipbus_o
.
ipb_rdata
'range
)
:
=
(
others
=>
'0'
);
-- data registered onto IPBus clock
signal
s_ack
:
std_logic
:
=
'0'
;
-- -- IPBus ACK signal
COMPONENT
dummy_event_fifo
PORT
(
rst
:
IN
STD_LOGIC
;
wr_clk
:
IN
STD_LOGIC
;
rd_clk
:
IN
STD_LOGIC
;
din
:
IN
STD_LOGIC_VECTOR
(
g_EVENT_DATA_WIDTH
-1
DOWNTO
0
);
wr_en
:
IN
STD_LOGIC
;
rd_en
:
IN
STD_LOGIC
;
dout
:
OUT
STD_LOGIC_VECTOR
(
g_EVENT_DATA_WIDTH
-1
DOWNTO
0
);
full
:
OUT
STD_LOGIC
;
almost_full
:
OUT
STD_LOGIC
;
empty
:
OUT
STD_LOGIC
;
almost_empty
:
OUT
STD_LOGIC
;
rd_data_count
:
OUT
STD_LOGIC_VECTOR
(
12
DOWNTO
0
);
prog_full
:
OUT
STD_LOGIC
);
END
COMPONENT
;
BEGIN
-----------------------------------------------------------------------------
-- IPBus IO
-----------------------------------------------------------------------------
--! Generate IPBus ACK
ipbus_ack
:
process
(
ipbus_clk_i
)
begin
if
rising_edge
(
ipbus_clk_i
)
then
s_ack
<=
ipbus_i
.
ipb_strobe
and
not
s_ack
;
end
if
;
end
process
ipbus_ack
;
ipbus_o
.
ipb_ack
<=
s_ack
;
--! Generate FIFO read enable
--! take high for one cycle ( when ipb_strobe goes high but before ACK goes
--high to follow it
s_fifo_rd_en
<=
'1'
when
ipbus_i
.
ipb_strobe
=
'1'
and
ipbus_i
.
ipb_write
=
'0'
and
ipbus_i
.
ipb_addr
(
1
downto
0
)
=
"00"
and
s_ack
=
'0'
else
'0'
;
ipbus_o
.
ipb_err
<=
'0'
;
--! Multiplex output data.
with
ipbus_i
.
ipb_addr
(
1
downto
0
)
select
ipbus_o
.
ipb_rdata
<=
s_fifo_dout
when
"00"
,
s_fifo_fill_level
when
"01"
,
s_fifo_status_ipb
when
"10"
,
(
others
=>
'1'
)
when
others
;
ipbus_write
:
process
(
ipbus_clk_i
)
begin
-- process ipbus_write
if
rising_edge
(
ipbus_clk_i
)
then
s_rst_fifo_ipb
<=
'0'
;
if
ipbus_i
.
ipb_strobe
=
'1'
and
ipbus_i
.
ipb_addr
(
1
downto
0
)
=
"10"
and
ipbus_i
.
ipb_write
=
'1'
then
s_rst_fifo_ipb
<=
'1'
;
end
if
;
-- Register data onto IPBus clock domain to ease timing closure.
s_fifo_status_ipb
<=
X"000000"
&
"000"
&
s_fifo_prog_full
&
s_fifo_full
&
s_fifo_almost_full
&
s_fifo_almost_empty
&
s_fifo_empty
;
s_fifo_fill_level
<=
X"0000"
&
"000"
&
s_rd_data_count
;
end
if
;
end
process
ipbus_write
;
rst_fifo_o
<=
s_rst_fifo_ipb
;
s_rst_fifo
<=
s_rst_fifo_ipb
or
logic_reset_i
;
-----------------------------------------------------------------------------
-- FIFO and fill-level calculation
-----------------------------------------------------------------------------
-- Instantiate a buffer to store the data. 64-bit on input, 32-bit on output.
--event_fifo : entity work.tlu_event_fifo
event_fifo
:
dummy_event_fifo
PORT
MAP
(
rst
=>
s_rst_fifo
,
wr_clk
=>
clk_4x_logic_i
,
rd_clk
=>
ipbus_clk_i
,
--din => event_data_i,
din
=>
event_data_i
,
wr_en
=>
data_strobe_i
,
rd_en
=>
s_fifo_rd_en
,
dout
=>
s_fifo_dout
,
full
=>
s_fifo_full
,
almost_full
=>
s_fifo_almost_full
,
empty
=>
s_fifo_empty
,
almost_empty
=>
s_fifo_almost_empty
,
rd_data_count
=>
s_rd_data_count
,
prog_full
=>
s_fifo_prog_full
);
buffer_full_o
<=
s_fifo_prog_full
;
END
ARCHITECTURE
rtl
;
EUDETdummy/hdl/top_EUDET_dummy.vhd
View file @
4ab568da
This diff is collapsed.
Click to expand it.
EUDETdummy/scripts/EUDETdummyaddrmap.xml
View file @
4ab568da
...
...
@@ -32,14 +32,14 @@
<node
id=
"i2c_cmdstatus"
address=
"0x4"
mask=
"0x000000ff"
permission=
"rw"
description=
""
/>
</node>
<!-- Not sure about the FillLevelFlags register -->
<!--
<node
id=
"eventBuffer"
address=
"0x4000"
description=
"Event buffer"
>
<node
id=
"EventFifoData"
address=
"0x0"
mode=
"non-incremental"
size=
"32000"
permission=
"r"
description=
""
/>
<node
id=
"EventFifoFillLevel"
address=
"0x1"
permission=
"r"
description=
""
/>
<node
id=
"EventFifoCSR"
address=
"0x2"
permission=
"rw"
description=
""
/>
<node
id=
"EventFifoFillLevelFlags"
address=
"0x3"
permission=
"r"
description=
""
/>
</node>
-->
<!-- Event formatter registers. Should be ok -->
<!--
<node id="Event_Formatter" address="0x5000" description="Event formatter configuration">
...
...
EUDETdummy/scripts/startEUDETdummy.py
View file @
4ab568da
...
...
@@ -66,6 +66,12 @@ if __name__ == "__main__":
logdata
=
True
EUDummy
.
start
(
logdata
)
time
.
sleep
(
0.2
)
nwords
=
int
(
EUDummy
.
getFifoLevel
()
)
print
nwords
myarray
=
EUDummy
.
getFifoData
(
nwords
)
for
iel
in
myarray
:
print
iel
>>
16
EUDummy
.
stop
()
# prompt = MyPrompt()
# prompt.prompt = '>> '
...
...
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