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AIDA-2020 TLU - Software
Commit 3c3ef5ce authored by Paolo Baesso's avatar Paolo Baesso
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Added the verbose option to clock configuration

parent def00b7c
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TLU_v1e/scripts/TLU_v1e.py
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......@@ -74,7 +74,7 @@ class TLU:
if (int(parsed_cfg.get(section_name, "CONFCLOCK"), 16)):
#clkRegList= self.zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
clkRegList= self.zeClock.parse_clk(parsed_cfg.get(section_name, "CLOCK_CFG_FILE"))
self.zeClock.writeConfiguration(clkRegList)######
self.zeClock.writeConfiguration(clkRegList, self.verbose)######
self.zeClock.checkDesignID()
......
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