# Edit the files in the IPBus repostitory to expose the 200MHz clock
sed -i 's/onehz);/onehz); clk_200_o<=clk200;/' ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
sed -i 's/clk125_o: out std_logic/clk125_o, clk_200_o: out std_logic/' ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
# Comment out the cfg signals in the IPBus constraints file enclustra_ax3_pm3.tcl
# In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
# In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
echo "Generating address table VHDL from XML file"