@@ -90,7 +90,9 @@ ARCHITECTURE rtl OF triggerLogic IS
signals_internal_trigger,s_internal_trigger_d:std_logic:='0';-- ! Strobes high for one clock cycle at intervals of s_internal_trigger_interval cycles
-- signal s_internal_trigger_timer : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- counter for internal trigger generation
signals_internal_trigger_timer,s_internal_trigger_timer_d:std_logic_vector(g_IPBUS_WIDTH-1downto0):=(others=>'0');-- counter for internal trigger generation and counter delay
signals_internal_trigger_active,s_internal_trigger_active_d,s_internal_trigger_active_ipb:std_logic:='0';-- ! Goes high when internal trigger is running.
signals_internal_trigger_active,s_internal_trigger_active_d,s_internal_trigger_active_ipb:std_logic:='0';--! Goes high when internal trigger is running.
signals_load_internal_trigger_counter:std_logic:='0';--! Goes high to load counter counts down to generate regular internal triggers
-- signal s_logic_reset , s_logic_reset_ipb : std_logic := '0'; -- ! Take high to reset counters etc.
signals_pre_veto_trigger,s_post_veto_trigger:std_logic:='0';-- ! Can't read from an output port so keep internal copy
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@@ -112,8 +114,8 @@ ARCHITECTURE rtl OF triggerLogic IS