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FMC DIO 5ch TTL a
Commit b0e208d2 authored by Javier Díaz's avatar Javier Díaz Committed by Miguel Jimenez Lopez
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including sdb support, moving i2c to wrcore

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modules/wrsw_dio/Manifest.py
View file @ b0e208d2
files = ["wrsw_dio_wb.vhd",
"xwrsw_dio.vhd",
"wrsw_dio.vhd",
"wrnic_sdb_pkg.vhd",
"pulse_gen_pl.vhd",
"immed_pulse_counter.vhd",
"immed_pulse_counter.vhd",
"dummy_time.vhd" ]
modules/wrsw_dio/wrnic_sdb_pkg.vhd 0 → 100644
View file @ b0e208d2
-------------------------------------------------------------------------------
-- Title : WhiteRabbit Network Interface Card
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrnic_sdb_pkg.vhd
-- Author : Javier Díaz
-- Company : Seven Solutions, UGR
-- Created : 2012-07-18
-- Last update: 2012-06-19
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Standard data bus (SDB) definitions for White Rabbit Network Interface Card (WR NIC=
-- #
-------------------------------------------------------------------------------
-- Copyright (c) 2012 Javier Díaz
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-07-18 1.0 jdiaz Created
--
-------------------------------------------------------------------------------
-- TODO: Move SDB devices definition to the corresponing package when merge
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
package wrnic_sdb_pkg is
-----------------------------------------------------------------------------
-- WR CORE --> TBD: move to wrcore_pkg
-----------------------------------------------------------------------------
constant c_xwr_core_sdb : t_sdb_product := (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000011",
version => x"00000003",
date => x"20120305",
name => "WR-CORE ");
-----------------------------------------------------------------------------
-- WR NIC
-----------------------------------------------------------------------------
constant c_xwrsw_nic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000001ffff", -- I think this is overestimated
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000012",
version => x"00000001",
date => x"20000101", -- UNKNOWN
name => "WR-NIC ")));
-----------------------------------------------------------------------------
-- WB VIC --> TBD: Move to wishbone_pkg
-----------------------------------------------------------------------------
constant c_xwb_vic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000013",
version => x"00000001",
date => x"20120113",
name => "WB-VIC-Int.Control ")));
-----------------------------------------------------------------------------
-- WR TXTSU --> TBD: Move to wrsw_txtsu_pkg
-----------------------------------------------------------------------------
constant c_xwrsw_txtsu_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000014",
version => x"00000001",
date => x"20120316",
name => "WR-TXTSU ")));
-----------------------------------------------------------------------------
-- WRSW DIO
-----------------------------------------------------------------------------
constant c_xwrsw_dio_sdb : t_sdb_product := (
vendor_id => x"00000000000075CB", -- SEVEN SOLUTIONS
device_id => x"00000002",
version => x"00000002",
date => x"20120720",
name => "WR-DIO-Core ");
-----------------------------------------------------------------------------
-- WRSW DIO REGISTERS - (basic slave from wbgen2)
-----------------------------------------------------------------------------
constant c_xwrsw_dio_wb_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"00000000000075CB", -- SEVEN SOLUTIONS
device_id => x"00000001",
version => x"00000002",
date => x"20120709",
name => "WR-DIO-Registers ")));
-------------------------------------------------------------------------------
-- WB ONEWIRE MASTER --> TBD: move wishbone_pkg
-- ISSUE: this element have two sdb definitions with different names, this one
-- and the one available at WR_CORE_PKG.
-- The definition need to be unique and be included into wishbone_pkg
-------------------------------------------------------------------------------
constant c_xwb_onewire_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"779c5443",
version => x"00000001",
date => x"20120305",
name => "WR-1Wire-master ")));
-------------------------------------------------------------------------------
-- WB I2C MASTER --> TBD: move to wishbone_pkg
-------------------------------------------------------------------------------
constant c_xwb_i2c_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"123c5443",
version => x"00000001",
date => x"20000101", -- UNKNOWN
name => "WB-I2C-Master ")));
-------------------------------------------------------------------------------
-- WB GPIO --> TBD: move to wishbone_pkg
-------------------------------------------------------------------------------
constant c_xwb_gpio_port_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"441c5143",
version => x"00000001",
date => x"20000101", -- UNKNOWN
name => "WB-GPIO-Port ")));
------------------------------------------------------------------------------
-- SDB re-declaration of bridges function to include product info
------------------------------------------------------------------------------
-- Use the f_xwb_bridge_*_sdb to bridge a crossbar to another
function f_xwb_bridge_product_manual_sdb( -- take a manual bus size
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address;
g_sdb_product : t_sdb_product) return t_sdb_bridge;
function f_xwb_bridge_product_layout_sdb( -- determine bus size from layout
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address;
g_sdb_product : t_sdb_product) return t_sdb_bridge;
end wrnic_sdb_pkg;
package body wrnic_sdb_pkg is
function f_xwb_bridge_product_manual_sdb(
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address;
g_sdb_product: t_sdb_product) return t_sdb_bridge
is
variable result : t_sdb_bridge;
begin
result.sdb_child := (others => '0');
result.sdb_child(c_wishbone_address_width-1 downto 0) := g_sdb_addr;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := (others => '0');
result.sdb_component.addr_last(c_wishbone_address_width-1 downto 0) := g_size;
result.sdb_component.product.vendor_id := g_sdb_product.vendor_id; -- GSI
result.sdb_component.product.device_id := g_sdb_product.device_id;
result.sdb_component.product.version := g_sdb_product.version;
result.sdb_component.product.date := g_sdb_product.date;
result.sdb_component.product.name := g_sdb_product.name;
return result;
end f_xwb_bridge_product_manual_sdb;
function f_xwb_bridge_product_layout_sdb(
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address;
g_sdb_product: t_sdb_product) return t_sdb_bridge
is
alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;
-- How much space does the ROM need?
constant c_used_entries : natural := c_layout'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
constant c_sdb_bytes : natural := c_sdb_device_length / 8;
constant c_rom_bytes : natural := c_rom_entries * c_sdb_bytes;
-- Step 2. Find the size of the bus
function f_bus_end return unsigned is
variable result : unsigned(63 downto 0);
variable sdb_component : t_sdb_component;
begin
if not g_wraparound then
result := (others => '0');
for i in 0 to c_wishbone_address_width-1 loop
result(i) := '1';
end loop;
else
-- The ROM will be an addressed slave as well
result := (others => '0');
result(c_wishbone_address_width-1 downto 0) := unsigned(g_sdb_addr);
result := result + to_unsigned(c_rom_bytes, 64) - 1;
for i in c_layout'range loop
sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
if unsigned(sdb_component.addr_last) > result then
result := unsigned(sdb_component.addr_last);
end if;
end loop;
-- round result up to a power of two -1
for i in 62 downto 0 loop
result(i) := result(i) or result(i+1);
end loop;
end if;
return result;
end f_bus_end;
constant bus_end : unsigned(63 downto 0) := f_bus_end;
begin
return f_xwb_bridge_product_manual_sdb(std_logic_vector(f_bus_end(c_wishbone_address_width-1 downto 0)), g_sdb_addr, g_sdb_product);
end f_xwb_bridge_product_layout_sdb;
end wrnic_sdb_pkg;
\ No newline at end of file
modules/wrsw_dio/wrsw_dio.vhd
View file @ b0e208d2
......@@ -3,34 +3,22 @@
-- Project : White Rabbit Network Interface
-------------------------------------------------------------------------------
-- File : wrsw_dio.vhd
-- Author : Rafael Rodriguez, Javier Díaz
-- Author : Javier Díaz
-- Company : Seven Solutions
-- Created : 2012-03-03
-- Last update: 2012-03-20
-- Created : 2012-07-25
-- Last update: 2012-07-25
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: The DIO core allows configuration of each one of the 5 channels of
-- the DIO mezzanine as input or output. For inputs, it provides an accurate seconds
-- time stamp (using seconds from the WRPC, not shown in the diagram) and
-- a host (PCIe) interrupt via the IRQ Gen block. For outputs, it allows the user
-- to schedule the generation of a pulse at a given future seconds time, or to generate
-- it immediately.
-- Description: Simulation file for the xwrsw_dio.vhd file
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-03-03 0.1 Rafa.r Created
-- 2012-03-08 0.2 Javier.d Added wrsw_dio_wb
-- 2012-07-05 0.3 Javier.d Midified wrsw_dio_wb, modified interface
-- 2012-07-25 0.1 JDiaz Created
-------------------------------------------------------------------------------
-- Memory map:
-- 0x000: DIO-ONEWIRE
-- 0x100: DIO-I2C
-- 0x200: DIO-GPIO
-- 0x300: DIO-REGISTERS
-- WARNING: only pipelined mode is supported (Intercon is pipelined only) - T.W.
library ieee;
use ieee.std_logic_1164.all;
......@@ -38,7 +26,7 @@ use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
entity wrsw_dio is
generic (
......@@ -69,684 +57,129 @@ entity wrsw_dio is
tm_seconds_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
-- Debug signals for chipscope
-------------------------------------------------------------------------------
-- Wishbone bus
-------------------------------------------------------------------------------
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
-- Debug signals for chipscope
TRIG0 : out std_logic_vector(31 downto 0);
TRIG1 : out std_logic_vector(31 downto 0);
TRIG2 : out std_logic_vector(31 downto 0);
TRIG3 : out std_logic_vector(31 downto 0);
TRIG3 : out std_logic_vector(31 downto 0)
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
-- wb_irq_data_fifo_o : out std_logic -- T.B.DELETED
);
end wrsw_dio;
architecture rtl of wrsw_dio is
-------------------------------------------------------------------------------
-- Component only for debugging (in order to generate seconds time)
-------------------------------------------------------------------------------
component dummy_time is
port(
clk_sys : in std_logic;
rst_n : in std_logic;
tm_utc : out std_logic_vector(39 downto 0);
tm_cycles : out std_logic_vector(27 downto 0));
end component;
-------------------------------------------------------------------------------
-- PULSE GENERATOR which produces a 1-tick-long pulse in its
-- output when the seconds time passed to it through a vector equals a
-- pre-programmed seconds time.
-------------------------------------------------------------------------------
component pulse_gen_pl is
-- DIO core
component xwrsw_dio
generic (
g_ref_clk_rate : integer := 125000000
);
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
clk_ref_i : in std_logic; -- timing reference clock
clk_sys_i : in std_logic; -- data output reference clock
rst_n_i : in std_logic; -- system reset
pulse_o : out std_logic; -- pulse output
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
dio_clk_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_onewire_b : inout std_logic;
dio_sdn_n_o : out std_logic;
dio_sdn_ck_n_o : out std_logic;
dio_led_top_o : out std_logic;
dio_led_bot_o : out std_logic;
dio_scl_b : inout std_logic;
dio_sda_b : inout std_logic;
dio_ga_o : out std_logic_vector(1 downto 0);
-------------------------------------------------------------------------------
-- Timing input (from WRPC), clk_ref_i domain
------------------------------------------------------------------------------
-- 1: time given on tm_utc_i and tm_cycles_i is valid (otherwise, don't
-- produce pulses and keep trig_ready_o line permamaently active)
tm_time_valid_i : in std_logic;
-- number of seconds
tm_utc_i : in std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles_i : in std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Time tag output (clk_sys_i domain)
---------------------------------------------------------------------------
-- 1: input is ready to accept next trigger time tag
trig_ready_o : out std_logic;
-- time at which the pulse will be produced + a single-cycle strobe to
-- latch it in
trig_utc_i : in std_logic_vector(39 downto 0);
trig_cycles_i : in std_logic_vector(27 downto 0);
trig_valid_p1_i : in std_logic;
pulse_length_i : in std_logic_vector(27 downto 0)
);
end component;
-------------------------------------------------------------------------------
-- PULSE STAMPER which associates a time-tag with an asyncrhonous
-- input pulse.
-------------------------------------------------------------------------------
component pulse_stamper is
generic (
-- reference clock frequency
g_ref_clk_rate : integer := 125000000
);
port(
clk_ref_i : in std_logic; -- timing reference clock
clk_sys_i : in std_logic; -- data output reference clock
rst_n_i : in std_logic; -- system reset
pulse_a_i : in std_logic; -- pulses to be stamped
-------------------------------------------------------------------------------
-- Timing input (from WRPC), clk_ref_i domain
------------------------------------------------------------------------------
-- 1: time given on tm_seconds_i and tm_cycles_i is valid (otherwise, don't timestamp)
tm_time_valid_i : in std_logic;
-- number of seconds
tm_utc_i : in std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_seconds_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Time tag output (clk_sys_i domain)
---------------------------------------------------------------------------
tag_utc_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
-- single-cycle pulse: strobe tag on tag_seconds_o and tag_cycles_o
tag_valid_p1_o : out std_logic
);
end component;
component immed_pulse_counter is
generic (
-- reference clock frequency
pulse_length_width : integer := 28
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic; -- asynchronous system reset
pulse_start_i : in std_logic; -- strobe for pulse generation
pulse_length_i : in std_logic_vector(pulse_length_width-1 downto 0);
pulse_output_o : out std_logic
);
end component;
component wrsw_dio_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_asyn_i : in std_logic;
-- FIFO write request
dio_tsf0_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf0_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf0_wr_empty_o : out std_logic;
dio_tsf0_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_0_i : in std_logic;
-- FIFO write request
dio_tsf1_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf1_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf1_wr_empty_o : out std_logic;
dio_tsf1_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_1_i : in std_logic;
-- FIFO write request
dio_tsf2_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf2_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf2_wr_empty_o : out std_logic;
dio_tsf2_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_2_i : in std_logic;
-- FIFO write request
dio_tsf3_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf3_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf3_wr_empty_o : out std_logic;
dio_tsf3_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_3_i : in std_logic;
-- FIFO write request
dio_tsf4_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf4_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf4_wr_empty_o : out std_logic;
dio_tsf4_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_4_i : in std_logic;
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trig0_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trigh0_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
dio_cyc0_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trig1_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trigh1_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
dio_cyc1_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trig2_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trigh2_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
dio_cyc2_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trig3_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trigh3_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
dio_cyc3_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trig4_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'outmode' in reg: 'FMC-DIO output configuration register. '
dio_out_mode_o : out std_logic_vector(4 downto 0);
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch1_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch2_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch3_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch4_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO time trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(4 downto 0);
irq_trigger_ready_0_i : in std_logic;
irq_trigger_ready_1_i : in std_logic;
irq_trigger_ready_2_i : in std_logic;
irq_trigger_ready_3_i : in std_logic;
irq_trigger_ready_4_i : in std_logic;
-- Port for std_logic_vector field: 'number of ticks field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse length'
dio_prog0_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse length'
dio_prog1_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse length'
dio_prog2_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse length'
dio_prog3_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse length'
dio_prog4_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_pulse_imm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
dio_pulse_imm_1_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
dio_pulse_imm_2_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_pulse_imm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_pulse_imm_4_o : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_WB_SLAVES_DIO : integer := 4;
TRIG0 : out std_logic_vector(31 downto 0);
TRIG1 : out std_logic_vector(31 downto 0);
TRIG2 : out std_logic_vector(31 downto 0);
TRIG3 : out std_logic_vector(31 downto 0);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal gpio_out : std_logic_vector(31 downto 0);
signal gpio_in : std_logic_vector(31 downto 0);
signal gpio_oen : std_logic_vector(31 downto 0);
signal onewire_en : std_logic;
signal onewire_pwren : std_logic;
signal scl_pad_in, scl_pad_out, scl_pad_oen : std_logic;
signal sda_pad_in, sda_pad_out, sda_pad_oen : std_logic;
-- Pulse generator trigger registers signals
type t_seconds_array is array (4 downto 0) of std_logic_vector (39 downto 0);
type t_cycles_array is array (4 downto 0) of std_logic_vector (27 downto 0);
type t_pulselength_array is array (4 downto 0) of std_logic_vector (27 downto 0);
signal trig_seconds : t_seconds_array;
signal trig_cycles : t_cycles_array;
signal trig_valid_p1 : std_logic_vector (4 downto 0);
signal trig_ready : std_logic_vector (4 downto 0);
signal tag_seconds : t_seconds_array;
signal tag_cycles : t_cycles_array;
signal tag_valid_p1 : std_logic_vector (4 downto 0);
signal pulse_length : t_pulselength_array;
-- FIFO signals
signal dio_tsf_wr_req : std_logic_vector (4 downto 0);
signal dio_tsf_wr_full : std_logic_vector (4 downto 0);
signal dio_tsf_wr_empty : std_logic_vector (4 downto 0);
signal dio_tsf_tag_seconds : t_seconds_array;
signal dio_tsf_tag_cycles : t_cycles_array;
-- Fifos no-empty interrupts
signal irq_nempty : std_logic_vector (4 downto 0);
-- DEBUG SIGNALS FOR USING seconds time values from dummy_time instead WRPC
signal tm_seconds : std_logic_vector (39 downto 0);
signal tm_cycles : std_logic_vector (27 downto 0);
-- WB Crossbar
constant c_cfg_base_addr : t_wishbone_address_array(3 downto 0) :=
(0 => x"00000000", -- ONEWIRE
1 => x"00000100", -- I2C
2 => x"00000200", -- GPIO
3 => x"00000300"); -- PULSE GEN & STAMPER
constant c_cfg_base_mask : t_wishbone_address_array(3 downto 0) :=
(0 => x"00000f00",
1 => x"00000f00",
2 => x"00000f00",
3 => x"00000f00");
signal cbar_master_in : t_wishbone_master_in_array(c_WB_SLAVES_DIO-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0);
signal slave_bypass_i : t_wishbone_slave_in;
signal slave_bypass_o : t_wishbone_slave_out;
-- DIO related signals
signal dio_pulse : std_logic_vector(4 downto 0);
signal dio_pulse_prog : std_logic_vector(4 downto 0);
signal dio_pulse_immed : std_logic_vector(4 downto 0);
signal dio_pulse_immed_stb : std_logic_vector(4 downto 0);
signal dio_out_mode : std_logic_vector(4 downto 0);
signal wb_dio_irq : std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
);
end component; --DIO core
-------------------------------------------------------------------------------
-- rtl
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
-------------------------------------------------------------------------------
begin
-- Dummy counter for simulationg WRPC seconds time
U_dummy: dummy_time
port map(
clk_sys => clk_ref_i,
rst_n => rst_n_i,
tm_utc => tm_seconds,
tm_cycles => tm_cycles
);
------------------------------------------------------------------------------
-- GEN AND STAMPER
------------------------------------------------------------------------------
gen_pulse_modules : for i in 0 to 4 generate
U_pulse_gen : pulse_gen_pl
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_o => dio_pulse_prog(i),
-- DEBUG
tm_time_valid_i => '1',--tm_time_valid_i,
tm_utc_i => tm_seconds,--tm_utc_i,
tm_cycles_i => tm_cycles, --tm_cycles_i,
-- tm_time_valid_i => tm_time_valid_i,
-- tm_utc_i => tm_seconds_i,
-- tm_cycles_i => tm_cycles_i,
trig_ready_o => trig_ready(i),
trig_utc_i => trig_seconds(i),
trig_cycles_i => trig_cycles(i),
trig_valid_p1_i => trig_valid_p1(i),
pulse_length_i => pulse_length(i)
);
U_pulse_stamper : pulse_stamper
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_a_i => dio_in_i(i),
-- DEBUG
tm_time_valid_i => '1',--tm_time_valid_i,
tm_utc_i => tm_seconds, --tm_utc_i,
tm_cycles_i => tm_cycles, --tm_cycles_i,
-- tm_time_valid_i => tm_time_valid_i,
-- tm_utc_i => tm_seconds_i,
-- tm_cycles_i => tm_cycles_i,
tag_utc_o => tag_seconds(i),
tag_cycles_o => tag_cycles(i),
tag_valid_p1_o => tag_valid_p1(i));
end generate gen_pulse_modules;
------------------------------------------------------------------------------
-- WB ONEWIRE MASTER
------------------------------------------------------------------------------
U_Onewire : xwb_onewire_master
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_ports => 1)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cbar_master_out(0),
slave_o => cbar_master_in(0),
desc_o => open,
owr_pwren_o(0) => onewire_pwren,
owr_en_o(0) => onewire_en,
owr_i(0) => dio_onewire_b);
dio_onewire_b <= '0' when onewire_en = '1' else 'Z';
------------------------------------------------------------------------------
-- WB I2C MASTER
------------------------------------------------------------------------------
U_I2C : xwb_i2c_master
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cbar_master_out(1),
slave_o => cbar_master_in(1),
desc_o => open,
scl_pad_i => scl_pad_in,
scl_pad_o => scl_pad_out,
scl_padoen_o => scl_pad_oen,
sda_pad_i => sda_pad_in,
sda_pad_o => sda_pad_out,
sda_padoen_o => sda_pad_oen);
dio_scl_b <= scl_pad_out when scl_pad_oen = '0' else 'Z';
dio_sda_b <= sda_pad_out when sda_pad_oen = '0' else 'Z';
scl_pad_in <= dio_scl_b;
sda_pad_in <= dio_sda_b;
dio_ga_o<="00"; -- Innused because SPEC boards have these fmc signals to ground
------------------------------------------------------------------------------
-- WB GPIO PORT
------------------------------------------------------------------------------
U_GPIO : xwb_gpio_port
U_WRAPPER_DIO : xwrsw_dio
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_pins => 32,
g_with_builtin_tristates => false)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cbar_master_out(2),
slave_o => cbar_master_in(2),
desc_o => open,
gpio_b => open,
gpio_out_o => gpio_out,
gpio_in_i => gpio_in,
gpio_oen_o => gpio_oen);
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity)
------------------------------------------------------------------------------
-- WB Crossbar
------------------------------------------------------------------------------
WB_INTERCON : xwb_crossbar
generic map(
g_num_masters => 1,
g_num_slaves => 4,
g_registered => true,
-- Address of the slaves connected
g_address => c_cfg_base_addr,
g_mask => c_cfg_base_mask
)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
-- Master connections
slave_i(0) => slave_bypass_i,
slave_o(0) => slave_bypass_o,
-- Slave conenctions
master_i => cbar_master_in,
master_o => cbar_master_out
);
-- Irq form one slave is bypassed to the Master connection
slave_bypass_i.cyc <= slave_i.cyc;
slave_bypass_i.stb <= slave_i.stb;
slave_bypass_i.adr <= slave_i.adr;
slave_bypass_i.sel <= slave_i.sel;
slave_bypass_i.dat <= slave_i.dat;
slave_bypass_i.we <= slave_i.we;
slave_o.ack <= slave_bypass_o.ack;
--slave_o.err <= slave_bypass_o.err;
--slave_o.rty <= slave_bypass_o.rty;
slave_o.stall <= slave_bypass_o.stall;
slave_o.int <= wb_dio_irq;
slave_o.dat <= slave_bypass_o.dat;
immediate_output_with_pulse_length: for i in 0 to 4 generate
immediate_output_component: immed_pulse_counter
generic map (
pulse_length_width => 28
)
port map(
clk_i => clk_ref_i,
rst_n_i => rst_n_i,
pulse_start_i => dio_pulse_immed_stb(i),
pulse_length_i => pulse_length(i),
pulse_output_o => dio_pulse_immed(i)
);
end generate immediate_output_with_pulse_length;
gen_pio_assignment: for i in 0 to 4 generate
gpio_in(4*i) <= dio_in_i(i);
dio_pulse(i) <= '1' when dio_pulse_immed(i) = '1' else dio_pulse_prog(i);
dio_out_o(i) <= dio_pulse(i) when dio_out_mode(i) ='1' else gpio_out(4*i);
dio_oe_n_o(i) <= gpio_out(4*i+1);
dio_term_en_o(i) <= gpio_out(4*i+2);
end generate gen_pio_assignment;
dio_led_bot_o <= gpio_out(28);
dio_led_top_o <= gpio_out(27);
clk_sys_i => clk_sys_i,
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_i,
dio_clk_i => dio_clk_i,
dio_in_i => dio_in_i,
dio_out_o => dio_out_o,
dio_oe_n_o => dio_oe_n_o,
dio_term_en_o => dio_term_en_o,
dio_onewire_b => dio_onewire_b,
dio_sdn_n_o => dio_sdn_n_o,
dio_sdn_ck_n_o => dio_sdn_ck_n_o,
dio_led_top_o => dio_led_top_o,
dio_led_bot_o => dio_led_bot_o,
dio_scl_b => dio_scl_b,
dio_sda_b => dio_sda_b,
dio_ga_o => dio_ga_o,
tm_time_valid_i => tm_time_valid_i,
tm_seconds_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
slave_i => wb_in,
slave_o => wb_out
-- Chipscope, debugging signals
--TRIG0 => TRIG0,
--TRIG1 => TRIG1,
--TRIG2 => TRIG2,
--TRIG3 => TRIG3,
);
wb_in.cyc <= wb_cyc_i;
wb_in.stb <= wb_stb_i;
wb_in.we <= wb_we_i;
wb_in.sel <= wb_sel_i;
wb_in.adr <= wb_adr_i;
wb_in.dat <= wb_dat_i;
wb_dat_o <= wb_out.dat;
wb_ack_o <= wb_out.ack;
wb_stall_o <= wb_out.stall;
wb_irq_o <= wb_out.int;
gpio_in(29) <= dio_clk_i;
dio_sdn_ck_n_o <= gpio_out(30);
dio_sdn_n_o <= gpio_out(31);
------------------------------------------------------------------------------
-- WB seconds-BASED PULSE GENERATION & INPUT STAMPING
------------------------------------------------------------------------------
U_seconds_wbslave : wrsw_dio_wb
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => cbar_master_out(3).adr(7 downto 2), -- only word acesses are available
wb_dat_i => cbar_master_out(3).dat,
wb_dat_o => cbar_master_in(3).dat,
wb_cyc_i => cbar_master_out(3).cyc,
wb_sel_i => cbar_master_out(3).sel,
wb_stb_i => cbar_master_out(3).stb,
wb_we_i => cbar_master_out(3).we,
wb_ack_o => cbar_master_in(3).ack,
wb_stall_o => cbar_master_in(3).stall,
-- Crossbar could not propagate interrupt lines of several slaves => signal bypass
wb_int_o => wb_dio_irq,
clk_asyn_i => clk_ref_i,
dio_tsf0_wr_req_i => dio_tsf_wr_req(0),
dio_tsf0_wr_full_o => dio_tsf_wr_full(0),
dio_tsf0_wr_empty_o => dio_tsf_wr_empty(0),
dio_tsf0_tag_seconds_i => dio_tsf_tag_seconds(0)(31 downto 0),
dio_tsf0_tag_secondsh_i => dio_tsf_tag_seconds(0)(39 downto 32),
dio_tsf0_tag_cycles_i => dio_tsf_tag_cycles(0),
irq_nempty_0_i => irq_nempty(0),
dio_tsf1_wr_req_i => dio_tsf_wr_req(1),
dio_tsf1_wr_full_o => dio_tsf_wr_full(1),
dio_tsf1_wr_empty_o => dio_tsf_wr_empty(1),
dio_tsf1_tag_seconds_i => dio_tsf_tag_seconds(1)(31 downto 0),
dio_tsf1_tag_secondsh_i => dio_tsf_tag_seconds(1)(39 downto 32),
dio_tsf1_tag_cycles_i => dio_tsf_tag_cycles(1),
irq_nempty_1_i => irq_nempty(1),
dio_tsf2_wr_req_i => dio_tsf_wr_req(2),
dio_tsf2_wr_full_o => dio_tsf_wr_full(2),
dio_tsf2_wr_empty_o => dio_tsf_wr_empty(2),
dio_tsf2_tag_seconds_i => dio_tsf_tag_seconds(2)(31 downto 0),
dio_tsf2_tag_secondsh_i => dio_tsf_tag_seconds(2)(39 downto 32),
dio_tsf2_tag_cycles_i => dio_tsf_tag_cycles(2),
irq_nempty_2_i => irq_nempty(2),
dio_tsf3_wr_req_i => dio_tsf_wr_req(3),
dio_tsf3_wr_full_o => dio_tsf_wr_full(3),
dio_tsf3_wr_empty_o => dio_tsf_wr_empty(3),
dio_tsf3_tag_seconds_i => dio_tsf_tag_seconds(3)(31 downto 0),
dio_tsf3_tag_secondsh_i => dio_tsf_tag_seconds(3)(39 downto 32),
dio_tsf3_tag_cycles_i => dio_tsf_tag_cycles(3),
irq_nempty_3_i => irq_nempty(3),
dio_tsf4_wr_req_i => dio_tsf_wr_req(4),
dio_tsf4_wr_full_o => dio_tsf_wr_full(4),
dio_tsf4_wr_empty_o => dio_tsf_wr_empty(4),
dio_tsf4_tag_seconds_i => dio_tsf_tag_seconds(4)(31 downto 0),
dio_tsf4_tag_secondsh_i => dio_tsf_tag_seconds(4)(39 downto 32),
dio_tsf4_tag_cycles_i => dio_tsf_tag_cycles(4),
irq_nempty_4_i => irq_nempty(4),
dio_trig0_seconds_o => trig_seconds(0)(31 downto 0),
dio_trigh0_seconds_o => trig_seconds(0)(39 downto 32),
dio_cyc0_cyc_o => trig_cycles(0),
dio_trig1_seconds_o => trig_seconds(1)(31 downto 0),
dio_trigh1_seconds_o => trig_seconds(1)(39 downto 32),
dio_cyc1_cyc_o => trig_cycles(1),
dio_trig2_seconds_o => trig_seconds(2)(31 downto 0),
dio_trigh2_seconds_o => trig_seconds(2)(39 downto 32),
dio_cyc2_cyc_o => trig_cycles(2),
dio_trig3_seconds_o => trig_seconds(3)(31 downto 0),
dio_trigh3_seconds_o => trig_seconds(3)(39 downto 32),
dio_cyc3_cyc_o => trig_cycles(3),
dio_trig4_seconds_o => trig_seconds(4)(31 downto 0),
dio_trigh4_seconds_o => trig_seconds(4)(39 downto 32),
dio_cyc4_cyc_o => trig_cycles(4),
dio_out_mode_o => dio_out_mode,
dio_latch_time_ch0_o => trig_valid_p1(0),
dio_latch_time_ch1_o => trig_valid_p1(1),
dio_latch_time_ch2_o => trig_valid_p1(2),
dio_latch_time_ch3_o => trig_valid_p1(3),
dio_latch_time_ch4_o => trig_valid_p1(4),
dio_trig_rdy_i => trig_ready,
irq_trigger_ready_0_i => trig_ready(0),
irq_trigger_ready_1_i => trig_ready(1),
irq_trigger_ready_2_i => trig_ready(2),
irq_trigger_ready_3_i => trig_ready(3),
irq_trigger_ready_4_i => trig_ready(4),
dio_prog0_pulse_length_o=> pulse_length(0),
dio_prog1_pulse_length_o=> pulse_length(1),
dio_prog2_pulse_length_o=> pulse_length(2),
dio_prog3_pulse_length_o=> pulse_length(3),
dio_prog4_pulse_length_o=> pulse_length(4),
dio_pulse_imm_0_o => dio_pulse_immed_stb(0),
dio_pulse_imm_1_o => dio_pulse_immed_stb(1),
dio_pulse_imm_2_o => dio_pulse_immed_stb(2),
dio_pulse_imm_3_o => dio_pulse_immed_stb(3),
dio_pulse_imm_4_o => dio_pulse_immed_stb(4)
);
-- seconds timestamped FIFO-no-empty interrupts
irq_fifos : for i in 0 to 4 generate
irq_nempty(i) <= not dio_tsf_wr_empty(i);
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dio_tsf_wr_req(i) <= '0';
dio_tsf_tag_seconds(i) <= (others => '0');
dio_tsf_tag_cycles(i) <= (others => '0');
else
if ((tag_valid_p1(i) = '1') AND (dio_tsf_wr_full(i)='0')) then
dio_tsf_wr_req(i) <='1';
dio_tsf_tag_seconds(i) <=tag_seconds(i);
dio_tsf_tag_cycles(i) <=tag_cycles(i);
else
dio_tsf_wr_req(i) <='0';
end if;
end if;
end if;
end process;
end generate irq_fifos;
-----------------------------------------------------------------------------------
------ signals for debugging
-----------------------------------------------------------------------------------
-- TRIG0 <= tag_utc(0)(31 downto 0);
-- TRIG1(27 downto 0) <= tag_cycles(0)(27 downto 0);
-- TRIG1(0) <= cbar_master_in(3).int;
-- TRIG2 <= tm_utc(31 downto 0);
-- TRIG3(2 downto 0) <= dio_in_i(0) & dio_out(0) & dio_pulse_immed(0);
--TRIG3(4 downto 0) <= dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0);
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
end rtl;
......
modules/wrsw_dio/xwrsw_dio.vhd
View file @ b0e208d2
......@@ -2,7 +2,7 @@
-- Title : DIO Core
-- Project : White Rabbit Network Interface
-------------------------------------------------------------------------------
-- File : wrsw_dio.vhd
-- File : xwrsw_dio.vhd
-- Author : Rafael Rodriguez, Javier Díaz
-- Company : Seven Solutions
-- Created : 2012-03-03
......@@ -17,13 +17,14 @@
-- to schedule the generation of a pulse at a given future seconds time, or to generate
-- it immediately.
-------------------------------------------------------------------------------
-- TODO:
-- TODO: Include wb adapter
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-03-03 0.1 Rafa.r Created
-- 2012-03-08 0.2 Javier.d Added wrsw_dio_wb
-- 2012-07-05 0.3 Javier.d Midified wrsw_dio_wb, modified interface
-- 2012-03-08 0.1 JDiaz Added wrsw_dio_wb
-- 2012-07-05 0.2 JDiaz Modified wrsw_dio_wb, modified interface
-- 2012-07-20 0.2 JDiaz Include sdb support
-------------------------------------------------------------------------------
-- Memory map:
-- 0x000: DIO-ONEWIRE
......@@ -38,7 +39,7 @@ use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.wrnic_sdb_pkg.all;
entity xwrsw_dio is
generic (
......@@ -68,16 +69,15 @@ entity xwrsw_dio is
tm_time_valid_i : in std_logic;
tm_seconds_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
-- Debug signals for chipscope
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Debug signals for chipscope
TRIG0 : out std_logic_vector(31 downto 0);
TRIG1 : out std_logic_vector(31 downto 0);
TRIG2 : out std_logic_vector(31 downto 0);
TRIG3 : out std_logic_vector(31 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
-- wb_irq_data_fifo_o : out std_logic -- T.B.DELETED
TRIG3 : out std_logic_vector(31 downto 0)
);
end xwrsw_dio;
......@@ -375,18 +375,14 @@ architecture rtl of xwrsw_dio is
signal tm_seconds : std_logic_vector (39 downto 0);
signal tm_cycles : std_logic_vector (27 downto 0);
-- WB Crossbar
constant c_cfg_base_addr : t_wishbone_address_array(3 downto 0) :=
(0 => x"00000000", -- ONEWIRE
1 => x"00000100", -- I2C
2 => x"00000200", -- GPIO
3 => x"00000300"); -- PULSE GEN & STAMPER
constant c_cfg_base_mask : t_wishbone_address_array(3 downto 0) :=
(0 => x"00000f00",
1 => x"00000f00",
2 => x"00000f00",
3 => x"00000f00");
-- WB SDB Crossbar
constant c_diobar_layout : t_sdb_record_array(3 downto 0) :=
(0 => f_sdb_embed_device(c_xwb_onewire_master_sdb , x"00000000"), -- ONEWIRE
1 => f_sdb_embed_device(c_xwb_i2c_master_sdb , x"00000100"), -- I2C
2 => f_sdb_embed_device(c_xwb_gpio_port_sdb , x"00000200"), -- GPIO
3 => f_sdb_embed_device(c_xwrsw_dio_wb_sdb , x"00000300") -- DIO REGISTERS
);
constant c_diobar_sdb_address : t_wishbone_address := x"00000400";
signal cbar_master_in : t_wishbone_master_in_array(c_WB_SLAVES_DIO-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0);
......@@ -444,7 +440,7 @@ begin
);
U_pulse_stamper : pulse_stamper
U_PULSE_STAMPER : pulse_stamper
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
......@@ -469,10 +465,10 @@ begin
------------------------------------------------------------------------------
-- WB ONEWIRE MASTER
------------------------------------------------------------------------------
U_Onewire : xwb_onewire_master
U_ONEWIRE : xwb_onewire_master
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_address_granularity => g_address_granularity,
g_num_ports => 1)
port map (
clk_sys_i => clk_sys_i,
......@@ -492,7 +488,7 @@ begin
U_I2C : xwb_i2c_master
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
g_address_granularity => g_address_granularity
)
port map (
......@@ -522,7 +518,7 @@ begin
U_GPIO : xwb_gpio_port
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_address_granularity => g_address_granularity,
g_num_pins => 32,
g_with_builtin_tristates => false)
port map (
......@@ -539,26 +535,26 @@ begin
------------------------------------------------------------------------------
-- WB Crossbar
------------------------------------------------------------------------------
WB_INTERCON : xwb_crossbar
WB_DIO_INTERCON : xwb_sdb_crossbar
generic map(
g_num_masters => 1,
g_num_slaves => 4,
g_registered => true,
-- Address of the slaves connected
g_address => c_cfg_base_addr,
g_mask => c_cfg_base_mask
g_wraparound => true,
g_layout => c_diobar_layout,
g_sdb_addr => c_diobar_sdb_address
)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
-- Master connections
slave_i(0) => slave_bypass_i,
slave_o(0) => slave_bypass_o,
-- Slave conenctions
master_i => cbar_master_in,
master_o => cbar_master_out
);
);
-- Irq form one slave is bypassed to the Master connection
slave_bypass_i.cyc <= slave_i.cyc;
slave_bypass_i.stb <= slave_i.stb;
......@@ -604,9 +600,9 @@ begin
dio_sdn_n_o <= gpio_out(31);
------------------------------------------------------------------------------
-- WB seconds-BASED PULSE GENERATION & INPUT STAMPING
-- WB DIO control registers
------------------------------------------------------------------------------
U_seconds_wbslave : wrsw_dio_wb
U_DIO_REGISTERS : wrsw_dio_wb
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
......
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