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- 5 input/output ports (Lemo 00 connectors)
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- Output levels: LVTTL, capable of driving +3.3 V over a 50-Ohm load.
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At power-up the outputs should be in Hi-Z state
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At power-up the outputs are in Hi-Z state (V1-2 and higher)
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- Input levels: any logic standard from Vih = 1 V to Vih = 5 V
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(programmable threshold)
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- Output Rise/fall times: max. 2 ns
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- Input bandwidth: min. 200 MHz
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- Programmable 50-Ohm input termination in each channel
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- LVDS I/O on the carrier side
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- One of the inputs shall be capable of driving a global clock net in
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the carrier's FPGA
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- Inputs need to be protected against +15V pulses with a pulse width
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of at least 10us @ 50Hz (with protection diodes if possible)
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- Withstands a continuous short-circuit on all the outputs at the same
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time (see
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[Issue 491](https://www.ohwr.org/project/fmc-dio-5chttla/issues/9))
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- One of the inputs is capable of driving a global clock net in the
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carrier's FPGA
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- Inputs protected against +15V pulses with a pulse width of up to
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10us @
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50Hz
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## Block diagram
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[Creotech](http://creotech.pl/), Poland
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- [INCAA Computers](http://incaacomputers.nl), Netherlands.
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### General question about project
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### Project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN - General
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question about project
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- Tom Wlostowski - CERN - Designer
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-----
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| ... | ... | @@ -103,12 +103,17 @@ dio\_small.jpg |
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<td>13-04-2012</td>
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<td>First version of Production test program written and documented in [PTS project](https://www.ohwr.org/project/pts/tree/master/test/fmcdio5chttla).</td>
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</tr>
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<tr class="odd">
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<td>15-08-2012</td>
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<td>V2-0 design being made to solve known Issues. V1-2 solves <a href="https://www.ohwr.org/project/fmc-dio-5chttla/issues/10">issue 487</a>.<br />
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Removed "withstands output shorted" spec: it works but is out of spec of driver IC.</td>
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</tr>
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</tbody>
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</table>
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-----
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Tom Wlostowski, Erik van der Bij - 25 June 2012
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Tom Wlostowski, Erik van der Bij - 15 August 2012
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