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## Functional specifications
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- 5 TTL-compatible I/Os.
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- 5 input/output ports (Lemo 00 connectors)
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- Output levels: LVTTL, capable of driving +3.3 V over a 50-Ohm load.
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At power-up the outputs should be in Hi-Z state.
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- Input levels: any logic standard from Vih = 1 V to Vih = 5 V
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(programmable threshold).
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- Output Rise/fall times: max. 2 ns
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- Input bandwidth: min. 200 MHz
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- Programmable 50-Ohm input termination in each channel.
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- External inputs need to be protected against +15V pulses with a
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pulse width of at least 10us @ 50Hz (with protection diodes if
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possible).
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- LVDS I/O on the carrier side.
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- One of the inputs shall be capable of driving a global clock net in
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the carrier's FPGA.
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- Inputs need to be protected against +15V pulses with a pulse width
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of at least 10us @ 50Hz (with protection diodes if possible).
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- Need to withstand a continuous short-circuit on all the outputs at
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the same time.
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- Output standard: 50 Ohm TTL drivers (with 2V/ns or faster rising
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edges). At power-up the default output state is low, with no
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glitches.
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## Project Status
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