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carrier's FPGA.
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- Inputs and outputs protected against +15V pulses with a pulse width
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of up to 10us @ 50Hz.
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- 4-layer
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PCB
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- 4-layer PCB
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- **NOTE:** *This board (up to v2.0) uses EEPROM that is not compatible with VITA 57.1 standard and thus carriers might have difficulties reading configuration from it, see [details](https://ohwr.org/project/fmc-projects/wikis/eeprom_24c02).*
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## Block diagram
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| ... | ... | @@ -85,7 +86,7 @@ PCB |
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-----
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Tom Wlostowski, Erik van der Bij - 31 January 2020
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Tom Wlostowski, Erik van der Bij, Maciej Lipinski - 11 May 2021
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| ... | ... | |
