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@@ -16,16 +16,16 @@ dio\_small.jpg
   - Output levels: LVTTL, capable of driving +2.5 V over a 50-Ohm load.
     At power-up the outputs are in Hi-Z state.
   - Input levels: any logic standard from Vih = 1 V to Vih = 5 V
-    (programmable threshold)
-  - Output Rise/fall times: max. 2 ns
-  - I/O bandwidth: 200 MHz
-  - Programmable 50-Ohm input termination in each channel
-  - LVDS I/O on the carrier side
+    (programmable threshold).
+  - Output Rise/fall times: max. 2 ns.
+  - I/O bandwidth: 200 MHz.
+  - Programmable 50-Ohm input termination in each channel.
+  - LVDS I/O on the carrier side.
   - One of the inputs is capable of driving a global clock net in the
-    carrier's FPGA
+    carrier's FPGA.
   - Inputs and outputs protected against +15V pulses with a pulse width
     of up to 10us @
-50Hz
+50Hz.
 
 ## Block diagram  
 ![](/uploads/2d0b0f455ea9fd3936c518b4d07a6173/block_diagram.jpg)
@@ -124,7 +124,7 @@ Removed "withstands output shorted" spec: it works but is out of spec
 </tr>
 <tr class="even">
 <td>25-10-2012</td>
-<td>Review of V2-0 planned.</td>
+<td><a href="Review20121025">Review</a> of V2-0.</td>
 </tr>
 </tbody>
 </table>