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Tomasz Wlostowski authored
hdl/syn/spec: updated the WR core builtin firmware to the 2.1 official release. Enabled synthesis with embedded firmware by default.
cec52178
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Manifest.py | ||
spec_reset_gen.vhd | ||
spec_serial_dac.vhd | ||
spec_serial_dac_arb.vhd | ||
spec_top.ucf | ||
spec_top.vhd | ||
synthesis_descriptor.vhd |