hdl: fd_delay_channel_driver.vhd: fixed RCR.CONT bit detection (now the core can…

hdl: fd_delay_channel_driver.vhd: fixed RCR.CONT bit detection (now the core can produce continuous waveforms)

hdl: fd_delay_channel_driver.vhd: fixed RCR.CONT bit detection (now the core can…
hdl: fd_delay_channel_driver.vhd: fixed RCR.CONT bit detection (now the core can produce continuous waveforms)
feae54fb · Tomasz Wlostowski · 8f422f8f · feae54fb
Commit feae54fb authored Feb 29, 2012 by Tomasz Wlostowski
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fd_delay_channel_driver.vhd hdl/rtl/fd_delay_channel_driver.vhd +3 -3

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--- a/hdl/rtl/fd_delay_channel_driver.vhd
+++ b/hdl/rtl/fd_delay_channel_driver.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-24
-- Last update: 2012-02-26
+-- Last update: 2012-02-29
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -572,12 +572,12 @@ begin
            delay_pulse0_o <= '0';
            delay_pulse1_o <= '0';
-            if(pulse_count = 0) then
+            if(pulse_count = 0 and rep_cont_int = '0') then
              state                  <= IDLE;
              delay_idle_o           <= '1';
              regs_out.dcr_pg_trig_i <= '1';
            else
-              regs_out.dcr_pg_trig_i <= rep_cont_int;
+              regs_out.dcr_pg_trig_i <= '1';
              if(no_fine_int = '1') then
                state <= WAIT_START_PULSE;
              else