<br>0: channel is disabled<br> 1: channel is enabled
<li><b>
MODE
</b>[<i>read/write</i>]: Delay mode select
<br>0: Channel will work as a delay generator, producing delayed copies of pulses comming to the trigger input<br>1: Channel will work as a programmable pulse generator - producing a pulse which begins at UTC time [U_START, C_START, F_START] and ends at [U_END, C_END, F_END].<br><b>Warning:</b> MODE_DLY bit can be safely set only when the TDC and the delay logic are disabled (i.e. when GCR.BYPASS = 1)
<li><b>
PG_ARM
</b>[<i>read/write</i>]: Pulse generator arm
<br>write 1: arms the pulse generator. <br> write 0: no effect.<br> Note that the time written to [U/C/F]START must be bigger by at least 200 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much bigger, as it's affected by the non-determinism of the operating system.
<li><b>
PG_TRIG
</b>[<i>read-only</i>]: Pulse generator triggered
<br>read 1: pulse generator has been triggered and produced a pulse<br> read 0: pulse generator is busy or hasn't triggered yet
<li><b>
UPDATE
</b>[<i>write-only</i>]: Start Delay Update
<br>write 1: Starts delay update procedure. The start and end times from [U/C/F][START/END] will be transferred in an atomic way to the internal delay/pulse generator registers<br> write 0: no effect.
<li><b>
UPD_DONE
</b>[<i>read-only</i>]: Delay Update Done
<br>read 1: The delays from [U/C/F][START/END] have been loaded into internal registers<br> read 0: update operation in progress
<li><b>
FORCE_DLY
</b>[<i>write-only</i>]: Force Calibration Delay
<br>write 1: preloads the delay line with the contents of FRR register. Used for self-calibration purposes.<br> write 0: no effect
<li><b>
NO_FINE
</b>[<i>read/write</i>]: Disable Fine Part update
<br>write 1: disables updating of the fine part of the pulse delay to allow for producing faster signals (i.e. pulse width/spacing <200ns),atthecostoflessaccuratewidth/spacingcontrol(multipleof4ms).<br>write 0: normal operation. Pulse width/spacing must be at least 200 ns.
</ul>
<aname="FRR"></a>
<h3><aname="sect_3_2">3.2. Fine Range Register</a></h3>
<tablecellpadding=0cellspacing=0border=0>
<tr>
<td>
<b>HW prefix: </b>
</td>
<tdclass="td_code">
fd_channel_frr
</td>
</tr>
<tr>
<td>
<b>HW address: </b>
</td>
<tdclass="td_code">
0x1
</td>
</tr>
<tr>
<td>
<b>C prefix: </b>
</td>
<tdclass="td_code">
FRR
</td>
</tr>
<tr>
<td>
<b>C offset: </b>
</td>
<tdclass="td_code">
0x4
</td>
</tr>
</table>
<p>
Delay line tap setting at which the line generates an 8 ns (one cycle) longer delay than when set to 0.
<h3><aname="sect_3_5">3.5. Pulse start time / offset (8 ns cycles)</a></h3>
<tablecellpadding=0cellspacing=0border=0>
<tr>
<td>
<b>HW prefix: </b>
</td>
<tdclass="td_code">
fd_channel_c_start
</td>
</tr>
<tr>
<td>
<b>HW address: </b>
</td>
<tdclass="td_code">
0x4
</td>
</tr>
<tr>
<td>
<b>C prefix: </b>
</td>
<tdclass="td_code">
C_START
</td>
</tr>
<tr>
<td>
<b>C offset: </b>
</td>
<tdclass="td_code">
0x10
</td>
</tr>
</table>
<p>
Sub-second part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.
<h3><aname="sect_3_6">3.6. Pulse start time / offset (sub-cycle fine part)</a></h3>
<tablecellpadding=0cellspacing=0border=0>
<tr>
<td>
<b>HW prefix: </b>
</td>
<tdclass="td_code">
fd_channel_f_start
</td>
</tr>
<tr>
<td>
<b>HW address: </b>
</td>
<tdclass="td_code">
0x5
</td>
</tr>
<tr>
<td>
<b>C prefix: </b>
</td>
<tdclass="td_code">
F_START
</td>
</tr>
<tr>
<td>
<b>C offset: </b>
</td>
<tdclass="td_code">
0x14
</td>
</tr>
</table>
<p>
Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8ns>: 0 = 0 ps, 4095 = 7999 ps.
<h3><aname="sect_3_9">3.9. Pulse end time / offset (8 ns cycles)</a></h3>
<tablecellpadding=0cellspacing=0border=0>
<tr>
<td>
<b>HW prefix: </b>
</td>
<tdclass="td_code">
fd_channel_c_end
</td>
</tr>
<tr>
<td>
<b>HW address: </b>
</td>
<tdclass="td_code">
0x8
</td>
</tr>
<tr>
<td>
<b>C prefix: </b>
</td>
<tdclass="td_code">
C_END
</td>
</tr>
<tr>
<td>
<b>C offset: </b>
</td>
<tdclass="td_code">
0x20
</td>
</tr>
</table>
<p>
Sub-second part of the pulse endabsolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.
<h3><aname="sect_3_10">3.10. Pulse end time / offset (sub-cycle fine part)</a></h3>
<tablecellpadding=0cellspacing=0border=0>
<tr>
<td>
<b>HW prefix: </b>
</td>
<tdclass="td_code">
fd_channel_f_end
</td>
</tr>
<tr>
<td>
<b>HW address: </b>
</td>
<tdclass="td_code">
0x9
</td>
</tr>
<tr>
<td>
<b>C prefix: </b>
</td>
<tdclass="td_code">
F_END
</td>
</tr>
<tr>
<td>
<b>C offset: </b>
</td>
<tdclass="td_code">
0x24
</td>
</tr>
</table>
<p>
Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8ns>: 0 = 0 ps, 4095 = 7999 ps.
<br>write 1: output will produce a contiguous square wave upon receptio of trigger pulse. The generation can be aborted by disabling the channel (DCRx.ENABLE = 0)<br> write 0: output will produce trains of REP_CNT+1 pulses.
