hdl/rtl: FMC present bit & extra debugging registers added to WB slaves

d98201c2 · Tomasz Wlostowski · 9121896b · d98201c2 · d98201c2 · d98201c2
Commit d98201c2 authored Apr 11, 2012 by Tomasz Wlostowski
8 changed files
--- a/hdl/include/regs/fd_channel_regs.vh
+++ b/hdl/include/regs/fd_channel_regs.vh
+`define ADDR_FD_DCR                    6'h0
+`define FD_DCR_ENABLE_OFFSET 0
+`define FD_DCR_ENABLE 32'h00000001
+`define FD_DCR_MODE_OFFSET 1
+`define FD_DCR_MODE 32'h00000002
+`define FD_DCR_PG_ARM_OFFSET 2
+`define FD_DCR_PG_ARM 32'h00000004
+`define FD_DCR_PG_TRIG_OFFSET 3
+`define FD_DCR_PG_TRIG 32'h00000008
+`define FD_DCR_UPDATE_OFFSET 4
+`define FD_DCR_UPDATE 32'h00000010
+`define FD_DCR_UPD_DONE_OFFSET 5
+`define FD_DCR_UPD_DONE 32'h00000020
+`define FD_DCR_FORCE_DLY_OFFSET 6
+`define FD_DCR_FORCE_DLY 32'h00000040
+`define FD_DCR_NO_FINE_OFFSET 7
+`define FD_DCR_NO_FINE 32'h00000080
+`define ADDR_FD_FRR                    6'h4
+`define ADDR_FD_U_STARTH               6'h8
+`define ADDR_FD_U_STARTL               6'hc
+`define ADDR_FD_C_START                6'h10
+`define ADDR_FD_F_START                6'h14
+`define ADDR_FD_U_ENDH                 6'h18
+`define ADDR_FD_U_ENDL                 6'h1c
+`define ADDR_FD_C_END                  6'h20
+`define ADDR_FD_F_END                  6'h24
+`define ADDR_FD_U_DELTA                6'h28
+`define ADDR_FD_C_DELTA                6'h2c
+`define ADDR_FD_F_DELTA                6'h30
+`define ADDR_FD_RCR                    6'h34
+`define FD_RCR_REP_CNT_OFFSET 0
+`define FD_RCR_REP_CNT 32'h0000ffff
+`define FD_RCR_CONT_OFFSET 16
+`define FD_RCR_CONT 32'h00010000
--- a/hdl/include/regs/fd_main_regs.vh
+++ b/hdl/include/regs/fd_main_regs.vh
+`define ADDR_FD_RSTR                   8'h0
+`define FD_RSTR_RST_FMC_OFFSET 0
+`define FD_RSTR_RST_FMC 32'h00000001
+`define FD_RSTR_RST_CORE_OFFSET 1
+`define FD_RSTR_RST_CORE 32'h00000002
+`define FD_RSTR_LOCK_OFFSET 16
+`define FD_RSTR_LOCK 32'hffff0000
+`define ADDR_FD_IDR                    8'h4
+`define ADDR_FD_GCR                    8'h8
+`define FD_GCR_BYPASS_OFFSET 0
+`define FD_GCR_BYPASS 32'h00000001
+`define FD_GCR_INPUT_EN_OFFSET 1
+`define FD_GCR_INPUT_EN 32'h00000002
+`define FD_GCR_DDR_LOCKED_OFFSET 2
+`define FD_GCR_DDR_LOCKED 32'h00000004
+`define FD_GCR_FMC_PRESENT_OFFSET 3
+`define FD_GCR_FMC_PRESENT 32'h00000008
+`define ADDR_FD_TCR                    8'hc
+`define FD_TCR_DMTD_STAT_OFFSET 0
+`define FD_TCR_DMTD_STAT 32'h00000001
+`define FD_TCR_WR_ENABLE_OFFSET 1
+`define FD_TCR_WR_ENABLE 32'h00000002
+`define FD_TCR_WR_LOCKED_OFFSET 2
+`define FD_TCR_WR_LOCKED 32'h00000004
+`define FD_TCR_WR_PRESENT_OFFSET 3
+`define FD_TCR_WR_PRESENT 32'h00000008
+`define FD_TCR_WR_READY_OFFSET 4
+`define FD_TCR_WR_READY 32'h00000010
+`define FD_TCR_WR_LINK_OFFSET 5
+`define FD_TCR_WR_LINK 32'h00000020
+`define FD_TCR_CAP_TIME_OFFSET 6
+`define FD_TCR_CAP_TIME 32'h00000040
+`define FD_TCR_SET_TIME_OFFSET 7
+`define FD_TCR_SET_TIME 32'h00000080
+`define ADDR_FD_TM_SECH                8'h10
+`define ADDR_FD_TM_SECL                8'h14
+`define ADDR_FD_TM_CYCLES              8'h18
+`define ADDR_FD_TDR                    8'h1c
+`define ADDR_FD_TDCSR                  8'h20
+`define FD_TDCSR_WRITE_OFFSET 0
+`define FD_TDCSR_WRITE 32'h00000001
+`define FD_TDCSR_READ_OFFSET 1
+`define FD_TDCSR_READ 32'h00000002
+`define FD_TDCSR_EMPTY_OFFSET 2
+`define FD_TDCSR_EMPTY 32'h00000004
+`define FD_TDCSR_STOP_EN_OFFSET 3
+`define FD_TDCSR_STOP_EN 32'h00000008
+`define FD_TDCSR_START_DIS_OFFSET 4
+`define FD_TDCSR_START_DIS 32'h00000010
+`define FD_TDCSR_START_EN_OFFSET 5
+`define FD_TDCSR_START_EN 32'h00000020
+`define FD_TDCSR_STOP_DIS_OFFSET 6
+`define FD_TDCSR_STOP_DIS 32'h00000040
+`define FD_TDCSR_ALUTRIG_OFFSET 7
+`define FD_TDCSR_ALUTRIG 32'h00000080
+`define ADDR_FD_CALR                   8'h24
+`define FD_CALR_CAL_PULSE_OFFSET 0
+`define FD_CALR_CAL_PULSE 32'h00000001
+`define FD_CALR_CAL_PPS_OFFSET 1
+`define FD_CALR_CAL_PPS 32'h00000002
+`define FD_CALR_CAL_DMTD_OFFSET 2
+`define FD_CALR_CAL_DMTD 32'h00000004
+`define FD_CALR_PSEL_OFFSET 3
+`define FD_CALR_PSEL 32'h00000078
+`define FD_CALR_DMTD_FBSEL_OFFSET 7
+`define FD_CALR_DMTD_FBSEL 32'h00000080
+`define FD_CALR_DMTD_TAG_OFFSET 8
+`define FD_CALR_DMTD_TAG 32'h7fffff00
+`define FD_CALR_DMTD_TAG_RDY_OFFSET 31
+`define FD_CALR_DMTD_TAG_RDY 32'h80000000
+`define ADDR_FD_SPLLR                  8'h28
+`define FD_SPLLR_TAG_OFFSET 0
+`define FD_SPLLR_TAG 32'h000fffff
+`define FD_SPLLR_TAG_RDY_OFFSET 20
+`define FD_SPLLR_TAG_RDY 32'h00100000
+`define FD_SPLLR_MODE_OFFSET 21
+`define FD_SPLLR_MODE 32'h00200000
+`define ADDR_FD_SDACR                  8'h2c
+`define FD_SDACR_DAC_VAL_OFFSET 0
+`define FD_SDACR_DAC_VAL 32'h0000ffff
+`define ADDR_FD_ADSFR                  8'h30
+`define ADDR_FD_ATMCR                  8'h34
+`define FD_ATMCR_C_THR_OFFSET 0
+`define FD_ATMCR_C_THR 32'h0000000f
+`define FD_ATMCR_F_THR_OFFSET 4
+`define FD_ATMCR_F_THR 32'h07fffff0
+`define ADDR_FD_ASOR                   8'h38
+`define FD_ASOR_OFFSET_OFFSET 0
+`define FD_ASOR_OFFSET 32'h007fffff
+`define ADDR_FD_IECRAW                 8'h3c
+`define ADDR_FD_IECTAG                 8'h40
+`define ADDR_FD_IEPD                   8'h44
+`define FD_IEPD_RST_STAT_OFFSET 0
+`define FD_IEPD_RST_STAT 32'h00000001
+`define FD_IEPD_PDELAY_OFFSET 1
+`define FD_IEPD_PDELAY 32'h000001fe
+`define ADDR_FD_SCR                    8'h48
+`define FD_SCR_DATA_OFFSET 0
+`define FD_SCR_DATA 32'h00ffffff
+`define FD_SCR_SEL_DAC_OFFSET 24
+`define FD_SCR_SEL_DAC 32'h01000000
+`define FD_SCR_SEL_PLL_OFFSET 25
+`define FD_SCR_SEL_PLL 32'h02000000
+`define FD_SCR_SEL_GPIO_OFFSET 26
+`define FD_SCR_SEL_GPIO 32'h04000000
+`define FD_SCR_READY_OFFSET 27
+`define FD_SCR_READY 32'h08000000
+`define FD_SCR_CPOL_OFFSET 28
+`define FD_SCR_CPOL 32'h10000000
+`define FD_SCR_START_OFFSET 29
+`define FD_SCR_START 32'h20000000
+`define ADDR_FD_RCRR                   8'h4c
+`define ADDR_FD_TSBCR                  8'h50
+`define FD_TSBCR_CHAN_MASK_OFFSET 0
+`define FD_TSBCR_CHAN_MASK 32'h0000001f
+`define FD_TSBCR_ENABLE_OFFSET 5
+`define FD_TSBCR_ENABLE 32'h00000020
+`define FD_TSBCR_PURGE_OFFSET 6
+`define FD_TSBCR_PURGE 32'h00000040
+`define FD_TSBCR_RST_SEQ_OFFSET 7
+`define FD_TSBCR_RST_SEQ 32'h00000080
+`define FD_TSBCR_FULL_OFFSET 8
+`define FD_TSBCR_FULL 32'h00000100
+`define FD_TSBCR_EMPTY_OFFSET 9
+`define FD_TSBCR_EMPTY 32'h00000200
+`define FD_TSBCR_COUNT_OFFSET 10
+`define FD_TSBCR_COUNT 32'h003ffc00
+`define ADDR_FD_TSBIR                  8'h54
+`define FD_TSBIR_TIMEOUT_OFFSET 0
+`define FD_TSBIR_TIMEOUT 32'h000003ff
+`define FD_TSBIR_THRESHOLD_OFFSET 10
+`define FD_TSBIR_THRESHOLD 32'h003ffc00
+`define ADDR_FD_TSBR_SECH              8'h58
+`define ADDR_FD_TSBR_SECL              8'h5c
+`define ADDR_FD_TSBR_CYCLES            8'h60
+`define ADDR_FD_TSBR_FID               8'h64
+`define FD_TSBR_FID_CHANNEL_OFFSET 0
+`define FD_TSBR_FID_CHANNEL 32'h0000000f
+`define FD_TSBR_FID_FINE_OFFSET 4
+`define FD_TSBR_FID_FINE 32'h0000fff0
+`define FD_TSBR_FID_SEQID_OFFSET 16
+`define FD_TSBR_FID_SEQID 32'hffff0000
+`define ADDR_FD_I2CR                   8'h68
+`define FD_I2CR_SCL_OUT_OFFSET 0
+`define FD_I2CR_SCL_OUT 32'h00000001
+`define FD_I2CR_SDA_OUT_OFFSET 1
+`define FD_I2CR_SDA_OUT 32'h00000002
+`define FD_I2CR_SCL_IN_OFFSET 2
+`define FD_I2CR_SCL_IN 32'h00000004
+`define FD_I2CR_SDA_IN_OFFSET 3
+`define FD_I2CR_SDA_IN 32'h00000008
+`define ADDR_FD_TDER1                  8'h6c
+`define FD_TDER1_VCXO_FREQ_OFFSET 0
+`define FD_TDER1_VCXO_FREQ 32'hffffffff
+`define ADDR_FD_TDER2                  8'h70
+`define FD_TDER2_PELT_DRIVE_OFFSET 0
+`define FD_TDER2_PELT_DRIVE 32'hffffffff
+`define ADDR_FD_EIC_IDR                8'h80
+`define FD_EIC_IDR_TS_BUF_NOTEMPTY_OFFSET 0
+`define FD_EIC_IDR_TS_BUF_NOTEMPTY 32'h00000001
+`define FD_EIC_IDR_DMTD_SPLL_OFFSET 1
+`define FD_EIC_IDR_DMTD_SPLL 32'h00000002
+`define FD_EIC_IDR_SYNC_STATUS_OFFSET 2
+`define FD_EIC_IDR_SYNC_STATUS 32'h00000004
+`define ADDR_FD_EIC_IER                8'h84
+`define FD_EIC_IER_TS_BUF_NOTEMPTY_OFFSET 0
+`define FD_EIC_IER_TS_BUF_NOTEMPTY 32'h00000001
+`define FD_EIC_IER_DMTD_SPLL_OFFSET 1
+`define FD_EIC_IER_DMTD_SPLL 32'h00000002
+`define FD_EIC_IER_SYNC_STATUS_OFFSET 2
+`define FD_EIC_IER_SYNC_STATUS 32'h00000004
+`define ADDR_FD_EIC_IMR                8'h88
+`define FD_EIC_IMR_TS_BUF_NOTEMPTY_OFFSET 0
+`define FD_EIC_IMR_TS_BUF_NOTEMPTY 32'h00000001
+`define FD_EIC_IMR_DMTD_SPLL_OFFSET 1
+`define FD_EIC_IMR_DMTD_SPLL 32'h00000002
+`define FD_EIC_IMR_SYNC_STATUS_OFFSET 2
+`define FD_EIC_IMR_SYNC_STATUS 32'h00000004
+`define ADDR_FD_EIC_ISR                8'h8c
+`define FD_EIC_ISR_TS_BUF_NOTEMPTY_OFFSET 0
+`define FD_EIC_ISR_TS_BUF_NOTEMPTY 32'h00000001
+`define FD_EIC_ISR_DMTD_SPLL_OFFSET 1
+`define FD_EIC_ISR_DMTD_SPLL 32'h00000002
+`define FD_EIC_ISR_SYNC_STATUS_OFFSET 2
+`define FD_EIC_ISR_SYNC_STATUS 32'h00000004
--- a/hdl/rtl/doc/fd_main_regs.html
+++ b/hdl/rtl/doc/fd_main_regs.html
--- a/hdl/rtl/fd_channel_wbgen2_pkg.vhd
+++ b/hdl/rtl/fd_channel_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : fd_channel_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created        : Wed Feb 29 12:04:02 2012
+-- Created        : Wed Apr 11 11:05:22 2012
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
@@ -78,6 +78,7 @@ package fd_channel_wbgen2_pkg is
      );
    function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
 end package;
 package body fd_channel_wbgen2_pkg is
@@ -89,11 +90,23 @@ else
 return x;
 end if; 
 end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if; 
+end loop; 
+return tmp;
+end function;
 function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers is
 variable tmp: t_fd_channel_in_registers;
 begin
-tmp.dcr_pg_trig_i := left.dcr_pg_trig_i or right.dcr_pg_trig_i;
+tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
-tmp.dcr_upd_done_i := left.dcr_upd_done_i or right.dcr_upd_done_i;
+tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
 return tmp;
 end function;
 end package body;
--- a/hdl/rtl/fd_channel_wishbone_slave.vhd
+++ b/hdl/rtl/fd_channel_wishbone_slave.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : fd_channel_wishbone_slave.vhd
 -- Author         : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created        : Wed Feb 29 12:04:02 2012
+-- Created        : Wed Apr 11 11:05:22 2012
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb

--- a/hdl/rtl/fd_main_wbgen2_pkg.vhd
+++ b/hdl/rtl/fd_main_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : fd_main_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created        : Wed Feb 29 12:04:02 2012
+-- Created        : Wed Apr 11 11:05:21 2012
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
@@ -22,6 +22,7 @@ package fd_main_wbgen2_pkg is
  type t_fd_main_in_registers is record
    gcr_ddr_locked_i                         : std_logic;
+    gcr_fmc_present_i                        : std_logic;
    tcr_dmtd_stat_i                          : std_logic;
    tcr_wr_locked_i                          : std_logic;
    tcr_wr_present_i                         : std_logic;
@@ -53,11 +54,12 @@ package fd_main_wbgen2_pkg is
    tsbr_fid_seqid_i                         : std_logic_vector(15 downto 0);
    i2cr_scl_in_i                            : std_logic;
    i2cr_sda_in_i                            : std_logic;
-    i2cr_dbg_i                               : std_logic_vector(3 downto 0);
+    tder1_vcxo_freq_i                        : std_logic_vector(31 downto 0);
    end record;
  constant c_fd_main_in_registers_init_value: t_fd_main_in_registers := (
    gcr_ddr_locked_i => '0',
+    gcr_fmc_present_i => '0',
    tcr_dmtd_stat_i => '0',
    tcr_wr_locked_i => '0',
    tcr_wr_present_i => '0',
@@ -89,7 +91,7 @@ package fd_main_wbgen2_pkg is
    tsbr_fid_seqid_i => (others => '0'),
    i2cr_scl_in_i => '0',
    i2cr_sda_in_i => '0',
-    i2cr_dbg_i => (others => '0')
+    tder1_vcxo_freq_i => (others => '0')
    );
    -- Output registers (WB slave -> user design)
@@ -149,7 +151,7 @@ package fd_main_wbgen2_pkg is
      tsbir_threshold_o                        : std_logic_vector(11 downto 0);
      i2cr_scl_out_o                           : std_logic;
      i2cr_sda_out_o                           : std_logic;
-      i2cr_dbgout_o                            : std_logic_vector(11 downto 0);
+      tder2_pelt_drive_o                       : std_logic_vector(31 downto 0);
      end record;
    constant c_fd_main_out_registers_init_value: t_fd_main_out_registers := (
@@ -207,10 +209,11 @@ package fd_main_wbgen2_pkg is
      tsbir_threshold_o => (others => '0'),
      i2cr_scl_out_o => '0',
      i2cr_sda_out_o => '0',
-      i2cr_dbgout_o => (others => '0')
+      tder2_pelt_drive_o => (others => '0')
      );
    function "or" (left, right: t_fd_main_in_registers) return t_fd_main_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
 end package;
 package body fd_main_wbgen2_pkg is
@@ -222,42 +225,55 @@ else
 return x;
 end if; 
 end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if; 
+end loop; 
+return tmp;
+end function;
 function "or" (left, right: t_fd_main_in_registers) return t_fd_main_in_registers is
 variable tmp: t_fd_main_in_registers;
 begin
-tmp.gcr_ddr_locked_i := left.gcr_ddr_locked_i or right.gcr_ddr_locked_i;
+tmp.gcr_ddr_locked_i := f_x_to_zero(left.gcr_ddr_locked_i) or f_x_to_zero(right.gcr_ddr_locked_i);
-tmp.tcr_dmtd_stat_i := left.tcr_dmtd_stat_i or right.tcr_dmtd_stat_i;
+tmp.gcr_fmc_present_i := f_x_to_zero(left.gcr_fmc_present_i) or f_x_to_zero(right.gcr_fmc_present_i);
-tmp.tcr_wr_locked_i := left.tcr_wr_locked_i or right.tcr_wr_locked_i;
+tmp.tcr_dmtd_stat_i := f_x_to_zero(left.tcr_dmtd_stat_i) or f_x_to_zero(right.tcr_dmtd_stat_i);
-tmp.tcr_wr_present_i := left.tcr_wr_present_i or right.tcr_wr_present_i;
+tmp.tcr_wr_locked_i := f_x_to_zero(left.tcr_wr_locked_i) or f_x_to_zero(right.tcr_wr_locked_i);
-tmp.tcr_wr_ready_i := left.tcr_wr_ready_i or right.tcr_wr_ready_i;
+tmp.tcr_wr_present_i := f_x_to_zero(left.tcr_wr_present_i) or f_x_to_zero(right.tcr_wr_present_i);
-tmp.tcr_wr_link_i := left.tcr_wr_link_i or right.tcr_wr_link_i;
+tmp.tcr_wr_ready_i := f_x_to_zero(left.tcr_wr_ready_i) or f_x_to_zero(right.tcr_wr_ready_i);
-tmp.tm_sech_i := left.tm_sech_i or right.tm_sech_i;
+tmp.tcr_wr_link_i := f_x_to_zero(left.tcr_wr_link_i) or f_x_to_zero(right.tcr_wr_link_i);
-tmp.tm_secl_i := left.tm_secl_i or right.tm_secl_i;
+tmp.tm_sech_i := f_x_to_zero(left.tm_sech_i) or f_x_to_zero(right.tm_sech_i);
-tmp.tm_cycles_i := left.tm_cycles_i or right.tm_cycles_i;
+tmp.tm_secl_i := f_x_to_zero(left.tm_secl_i) or f_x_to_zero(right.tm_secl_i);
-tmp.tdr_i := left.tdr_i or right.tdr_i;
+tmp.tm_cycles_i := f_x_to_zero(left.tm_cycles_i) or f_x_to_zero(right.tm_cycles_i);
-tmp.tdcsr_empty_i := left.tdcsr_empty_i or right.tdcsr_empty_i;
+tmp.tdr_i := f_x_to_zero(left.tdr_i) or f_x_to_zero(right.tdr_i);
-tmp.calr_dmtd_tag_i := left.calr_dmtd_tag_i or right.calr_dmtd_tag_i;
+tmp.tdcsr_empty_i := f_x_to_zero(left.tdcsr_empty_i) or f_x_to_zero(right.tdcsr_empty_i);
-tmp.calr_dmtd_tag_rdy_i := left.calr_dmtd_tag_rdy_i or right.calr_dmtd_tag_rdy_i;
+tmp.calr_dmtd_tag_i := f_x_to_zero(left.calr_dmtd_tag_i) or f_x_to_zero(right.calr_dmtd_tag_i);
-tmp.spllr_tag_i := left.spllr_tag_i or right.spllr_tag_i;
+tmp.calr_dmtd_tag_rdy_i := f_x_to_zero(left.calr_dmtd_tag_rdy_i) or f_x_to_zero(right.calr_dmtd_tag_rdy_i);
-tmp.spllr_tag_rdy_i := left.spllr_tag_rdy_i or right.spllr_tag_rdy_i;
+tmp.spllr_tag_i := f_x_to_zero(left.spllr_tag_i) or f_x_to_zero(right.spllr_tag_i);
-tmp.iecraw_i := left.iecraw_i or right.iecraw_i;
+tmp.spllr_tag_rdy_i := f_x_to_zero(left.spllr_tag_rdy_i) or f_x_to_zero(right.spllr_tag_rdy_i);
-tmp.iectag_i := left.iectag_i or right.iectag_i;
+tmp.iecraw_i := f_x_to_zero(left.iecraw_i) or f_x_to_zero(right.iecraw_i);
-tmp.iepd_pdelay_i := left.iepd_pdelay_i or right.iepd_pdelay_i;
+tmp.iectag_i := f_x_to_zero(left.iectag_i) or f_x_to_zero(right.iectag_i);
-tmp.scr_data_i := left.scr_data_i or right.scr_data_i;
+tmp.iepd_pdelay_i := f_x_to_zero(left.iepd_pdelay_i) or f_x_to_zero(right.iepd_pdelay_i);
-tmp.scr_ready_i := left.scr_ready_i or right.scr_ready_i;
+tmp.scr_data_i := f_x_to_zero(left.scr_data_i) or f_x_to_zero(right.scr_data_i);
-tmp.rcrr_i := left.rcrr_i or right.rcrr_i;
+tmp.scr_ready_i := f_x_to_zero(left.scr_ready_i) or f_x_to_zero(right.scr_ready_i);
-tmp.tsbcr_full_i := left.tsbcr_full_i or right.tsbcr_full_i;
+tmp.rcrr_i := f_x_to_zero(left.rcrr_i) or f_x_to_zero(right.rcrr_i);
-tmp.tsbcr_empty_i := left.tsbcr_empty_i or right.tsbcr_empty_i;
+tmp.tsbcr_full_i := f_x_to_zero(left.tsbcr_full_i) or f_x_to_zero(right.tsbcr_full_i);
-tmp.tsbcr_count_i := left.tsbcr_count_i or right.tsbcr_count_i;
+tmp.tsbcr_empty_i := f_x_to_zero(left.tsbcr_empty_i) or f_x_to_zero(right.tsbcr_empty_i);
-tmp.tsbr_sech_i := left.tsbr_sech_i or right.tsbr_sech_i;
+tmp.tsbcr_count_i := f_x_to_zero(left.tsbcr_count_i) or f_x_to_zero(right.tsbcr_count_i);
-tmp.tsbr_secl_i := left.tsbr_secl_i or right.tsbr_secl_i;
+tmp.tsbr_sech_i := f_x_to_zero(left.tsbr_sech_i) or f_x_to_zero(right.tsbr_sech_i);
-tmp.tsbr_cycles_i := left.tsbr_cycles_i or right.tsbr_cycles_i;
+tmp.tsbr_secl_i := f_x_to_zero(left.tsbr_secl_i) or f_x_to_zero(right.tsbr_secl_i);
-tmp.tsbr_fid_channel_i := left.tsbr_fid_channel_i or right.tsbr_fid_channel_i;
+tmp.tsbr_cycles_i := f_x_to_zero(left.tsbr_cycles_i) or f_x_to_zero(right.tsbr_cycles_i);
-tmp.tsbr_fid_fine_i := left.tsbr_fid_fine_i or right.tsbr_fid_fine_i;
+tmp.tsbr_fid_channel_i := f_x_to_zero(left.tsbr_fid_channel_i) or f_x_to_zero(right.tsbr_fid_channel_i);
-tmp.tsbr_fid_seqid_i := left.tsbr_fid_seqid_i or right.tsbr_fid_seqid_i;
+tmp.tsbr_fid_fine_i := f_x_to_zero(left.tsbr_fid_fine_i) or f_x_to_zero(right.tsbr_fid_fine_i);
-tmp.i2cr_scl_in_i := left.i2cr_scl_in_i or right.i2cr_scl_in_i;
+tmp.tsbr_fid_seqid_i := f_x_to_zero(left.tsbr_fid_seqid_i) or f_x_to_zero(right.tsbr_fid_seqid_i);
-tmp.i2cr_sda_in_i := left.i2cr_sda_in_i or right.i2cr_sda_in_i;
+tmp.i2cr_scl_in_i := f_x_to_zero(left.i2cr_scl_in_i) or f_x_to_zero(right.i2cr_scl_in_i);
-tmp.i2cr_dbg_i := left.i2cr_dbg_i or right.i2cr_dbg_i;
+tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
+tmp.tder1_vcxo_freq_i := f_x_to_zero(left.tder1_vcxo_freq_i) or f_x_to_zero(right.tder1_vcxo_freq_i);
 return tmp;
 end function;
 end package body;
--- a/hdl/rtl/fd_main_wishbone_slave.vhd
+++ b/hdl/rtl/fd_main_wishbone_slave.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : fd_main_wishbone_slave.vhd
 -- Author         : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created        : Wed Feb 29 12:04:02 2012
+-- Created        : Wed Apr 11 11:05:21 2012
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
@@ -237,7 +237,7 @@ signal fd_main_tsbir_timeout_int                : std_logic_vector(9 downto 0);
 signal fd_main_tsbir_threshold_int              : std_logic_vector(11 downto 0);
 signal fd_main_i2cr_scl_out_int                 : std_logic      ;
 signal fd_main_i2cr_sda_out_int                 : std_logic      ;
-signal fd_main_i2cr_dbgout_int                  : std_logic_vector(11 downto 0);
+signal fd_main_tder2_pelt_drive_int             : std_logic_vector(31 downto 0);
 signal eic_idr_int                              : std_logic_vector(2 downto 0);
 signal eic_idr_write_int                        : std_logic      ;
 signal eic_ier_int                              : std_logic_vector(2 downto 0);
@@ -376,7 +376,7 @@ begin
      advance_rbuf_o <= '0';
      fd_main_i2cr_scl_out_int <= '0';
      fd_main_i2cr_sda_out_int <= '0';
-      fd_main_i2cr_dbgout_int <= "000000000000";
+      fd_main_tder2_pelt_drive_int <= "00000000000000000000000000000000";
      eic_idr_write_int <= '0';
      eic_ier_write_int <= '0';
      eic_isr_write_int <= '0';
@@ -549,7 +549,7 @@ begin
            rddata_reg(0) <= fd_main_gcr_bypass_int;
            rddata_reg(1) <= fd_main_gcr_input_en_int;
            rddata_reg(2) <= regs_i.gcr_ddr_locked_i;
-            rddata_reg(3) <= 'X';
+            rddata_reg(3) <= regs_i.gcr_fmc_present_i;
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
@@ -1101,14 +1101,27 @@ begin
            if (wb_we_i = '1') then
              fd_main_i2cr_scl_out_int <= wrdata_reg(0);
              fd_main_i2cr_sda_out_int <= wrdata_reg(1);
-              fd_main_i2cr_dbgout_int <= wrdata_reg(19 downto 8);
            end if;
            rddata_reg(0) <= fd_main_i2cr_scl_out_int;
            rddata_reg(1) <= fd_main_i2cr_sda_out_int;
            rddata_reg(2) <= regs_i.i2cr_scl_in_i;
            rddata_reg(3) <= regs_i.i2cr_sda_in_i;
-            rddata_reg(7 downto 4) <= regs_i.i2cr_dbg_i;
+            rddata_reg(4) <= 'X';
-            rddata_reg(19 downto 8) <= fd_main_i2cr_dbgout_int;
+            rddata_reg(5) <= 'X';
+            rddata_reg(6) <= 'X';
+            rddata_reg(7) <= 'X';
+            rddata_reg(8) <= 'X';
+            rddata_reg(9) <= 'X';
+            rddata_reg(10) <= 'X';
+            rddata_reg(11) <= 'X';
+            rddata_reg(12) <= 'X';
+            rddata_reg(13) <= 'X';
+            rddata_reg(14) <= 'X';
+            rddata_reg(15) <= 'X';
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
@@ -1123,6 +1136,19 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
+          when "011011" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.tder1_vcxo_freq_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "011100" => 
+            if (wb_we_i = '1') then
+              fd_main_tder2_pelt_drive_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= fd_main_tder2_pelt_drive_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
          when "100000" => 
            if (wb_we_i = '1') then
              eic_idr_write_int <= '1';
@@ -1325,6 +1351,7 @@ begin
 -- PLL Locked
+-- Mezzanice Present
 -- DMTD Clock Status
 -- WR Timing Enable
  regs_o.tcr_wr_enable_o <= fd_main_tcr_wr_enable_int;
@@ -1971,9 +1998,9 @@ begin
  regs_o.i2cr_sda_out_o <= fd_main_i2cr_sda_out_int;
 -- SCL Line in
 -- SDA Line in
-- Debug in
+-- VCXO Frequency
-- Debug out
+-- Peltier PWM drive
-  regs_o.i2cr_dbgout_o <= fd_main_i2cr_dbgout_int;
+  regs_o.tder2_pelt_drive_o <= fd_main_tder2_pelt_drive_int;
 -- extra code for reg/fifo/mem: Interrupt disable register
  eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
 -- extra code for reg/fifo/mem: Interrupt enable register

--- a/hdl/rtl/fd_main_wishbone_slave.wb
+++ b/hdl/rtl/fd_main_wishbone_slave.wb
@@ -132,6 +132,16 @@ peripheral {
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
+      field {
+         name = "Mezzanice Present";
+         description = "read 1: FMC card is present (PRSNT_L == 0)\
+         read 0: no FMC card in the slot (PRSNT_L == 1)";
+         prefix = "FMC_PRESENT";
+         type = BIT;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
+      };
   };
   reg {
@@ -886,25 +896,36 @@ write 0: DMTD pattern generation disabled.";
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
+   };
+   reg {
+      name = "Test/Debug register 1";
+      prefix = "TDER1";
      field {
-         name = "Debug in";
+         name = "VCXO Frequency";
-         prefix = "DBG";
+         prefix = "VCXO_FREQ";
+         size = 32;
         type = SLV;
-         size = 4;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
+   };
+   reg {
+      name = "Test/Debug register 1";
+      prefix = "TDER2";
      field {
-         name = "Debug out";
+         name = "Peltier PWM drive";
-         prefix = "DBGOUT";
+         prefix = "PELT_DRIVE";
+         size = 32;
         type = SLV;
-         size = 12;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
   };
   irq {