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FMC DEL 1ns 4cha
Commit c00e32c0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/rtl/fd_ring_buffer.vhd: fixed invalid DPRAM clock connection

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hdl/.gitignore
View file @ c00e32c0
......@@ -8,7 +8,5 @@ modelsim.ini
*.vstf
work
*.bak
syn/spec_1_1/*
syn/spec_wr_demo/*
syn/tests
syn/*
transcript
\ No newline at end of file
hdl/rtl/fd_ring_buffer.vhd
View file @ c00e32c0
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-02-20
-- Last update: 2012-05-01
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -191,7 +191,7 @@ begin -- behavioral
g_dual_clock => false)
port map (
rst_n_i => rst_n_sys_i,
clka_i => clk_ref_i,
clka_i => clk_sys_i,
bwea_i => (others => '1'),
wea_i => buf_write,
aa_i => std_logic_vector(buf_wr_ptr),
......
hdl/syn/spec/non_wr/spec_fine_delay.xise
View file @ c00e32c0
......@@ -836,219 +836,243 @@
<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../../../rtl/fd_csync_generator.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../rtl/fd_csync_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../../rtl/fine_delay_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../rtl/fine_delay_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdwb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../../../rtl/fd_main_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../rtl/fd_main_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file>
</files>
<bindings/>
......
hdl/testbench/top/Makefile
View file @ c00e32c0
......@@ -12,110 +12,62 @@ VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VERILOG_SRC := main.sv \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_cpu.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_addsub.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_top.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_instruction_unit.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_decoder.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_load_store_unit.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_adder.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_logic_op.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_shifter.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_multiplier.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_interrupt.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_dp_ram.v \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v \
VERILOG_OBJ := work/main/.main_sv \
work/lm32_cpu/.lm32_cpu_v \
work/lm32_addsub/.lm32_addsub_v \
work/lm32_top/.lm32_top_v \
work/lm32_instruction_unit/.lm32_instruction_unit_v \
work/lm32_decoder/.lm32_decoder_v \
work/lm32_load_store_unit/.lm32_load_store_unit_v \
work/lm32_adder/.lm32_adder_v \
work/lm32_logic_op/.lm32_logic_op_v \
work/lm32_shifter/.lm32_shifter_v \
work/lm32_multiplier/.lm32_multiplier_v \
work/lm32_interrupt/.lm32_interrupt_v \
work/lm32_dp_ram/.lm32_dp_ram_v \
work/sockit_owm/.sockit_owm_v \
work/spi_clgen/.spi_clgen_v \
work/spi_shift/.spi_shift_v \
work/spi_top/.spi_top_v \
work/lm32_allprofiles/.lm32_allprofiles_v \
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v \
work/jtag_cores/.jtag_cores_v \
work/lm32_adder/.lm32_adder_v \
work/lm32_addsub/.lm32_addsub_v \
work/lm32_dp_ram/.lm32_dp_ram_v \
work/lm32_logic_op/.lm32_logic_op_v \
work/lm32_ram/.lm32_ram_v \
work/lm32_shifter/.lm32_shifter_v \
work/lm32_multiplier/.lm32_multiplier_v \
work/jtag_tap/.jtag_tap_v \
VHDL_SRC := ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
VHDL_SRC := ../../platform/fd_ddr_driver.vhd \
../../platform/fd_ddr_pll.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../rtl/fd_channel_wbgen2_pkg.vhd \
../../rtl/fd_ts_adder.vhd \
../../rtl/fd_ts_normalizer.vhd \
../../rtl/fd_wbgen2_pkg.vhd \
../../rtl/fd_csync_generator.vhd \
../../rtl/fd_timestamper_stat_unit.vhd \
../../rtl/fd_acam_timestamp_postprocessor.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../rtl/fd_main_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../rtl/fine_delay_pkg.vhd \
../../rtl/fd_delay_line_arbiter.vhd \
../../rtl/fd_rearm_generator.vhd \
../../rtl/fd_reset_generator.vhd \
../../rtl/fd_spi_master.vhd \
../../rtl/fd_spi_dac_arbiter.vhd \
../../rtl/fd_delay_channel_driver.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core_private_pkg.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller_wb_slave.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/gn4124_core_pkg.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/l2p_arbiter.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/l2p_dma_master.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/p2l_decode32.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/p2l_dma_master.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/wbmaster32.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd \
../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/endpoint_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_softpll/softpll_wb.vhd \
../../ip_cores/wr-cores/modules/wr_softpll/wr_softpll.vhd \
../../ip_cores/wr-cores/modules/wrc_lm32/wrc_lm32.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_enc_8b10b.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_dec_8b10b.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_pcs_tbi.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_pcs_tbi.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_autonegotiation.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_pcs_tbi_mdio_wb.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_1000basex_pcs.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_crc_size_check.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_deframer.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_framer.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_flow_control.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_timestamping_unit.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rmon_counters.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_buffer.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_sync_detect.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_wishbone_controller.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_ts_counter.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/wrsw_endpoint.vhd \
../../ip_cores/wr-cores/modules/wrsw_pps_gen/pps_gen_wb.vhd \
../../ip_cores/wr-cores/modules/wrsw_pps_gen/wrsw_pps_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd \
../../rtl/fd_acam_timestamper.vhd \
../../rtl/fd_acam_timestamp_postprocessor.vhd \
../../rtl/fd_channel_wishbone_slave.vhd \
../../rtl/fd_timestamper_stat_unit.vhd \
../../rtl/fd_delay_channel_driver.vhd \
../../rtl/fd_ring_buffer.vhd \
../../rtl/fd_dmtd_insertion_calibrator.vhd \
../../rtl/timing/fd_dmtd_with_deglitcher.vhd \
../../rtl/timing/fd_hpll_period_detect.vhd \
../../rtl/fd_reset_generator.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
......@@ -123,12 +75,21 @@ VHDL_SRC := ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../rtl/fd_ring_buffer.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
../../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
../../rtl/fd_csync_generator.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../rtl/fine_delay_core.vhd \
../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
......@@ -137,112 +98,64 @@ VHDL_SRC := ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdwb_rom.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../rtl/fd_wishbone_slave.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/p2l_des.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
VHDL_OBJ := work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/genram_pkg/.genram_pkg_vhd \
../../rtl/fd_main_wishbone_slave.vhd \
VHDL_OBJ := work/fd_ddr_driver/.fd_ddr_driver_vhd \
work/fd_ddr_pll/.fd_ddr_pll_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/fd_channel_wbgen2_pkg/.fd_channel_wbgen2_pkg_vhd \
work/fd_ts_adder/.fd_ts_adder_vhd \
work/fd_ts_normalizer/.fd_ts_normalizer_vhd \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg_vhd \
work/fd_csync_generator/.fd_csync_generator_vhd \
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit_vhd \
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg_vhd \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/fine_delay_pkg/.fine_delay_pkg_vhd \
work/fd_delay_line_arbiter/.fd_delay_line_arbiter_vhd \
work/fd_rearm_generator/.fd_rearm_generator_vhd \
work/fd_reset_generator/.fd_reset_generator_vhd \
work/fd_spi_master/.fd_spi_master_vhd \
work/fd_spi_dac_arbiter/.fd_spi_dac_arbiter_vhd \
work/fd_delay_channel_driver/.fd_delay_channel_driver_vhd \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg_vhd \
work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd \
work/gn4124_core_pkg/.gn4124_core_pkg_vhd \
work/l2p_arbiter/.l2p_arbiter_vhd \
work/l2p_dma_master/.l2p_dma_master_vhd \
work/p2l_decode32/.p2l_decode32_vhd \
work/p2l_dma_master/.p2l_dma_master_vhd \
work/wbmaster32/.wbmaster32_vhd \
work/gtp_bitslide/.gtp_bitslide_vhd \
work/gtp_phase_align/.gtp_phase_align_vhd \
work/whiterabbitgtp_wrapper_tile/.whiterabbitgtp_wrapper_tile_vhd \
work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6_vhd \
work/dmtd_phase_meas/.dmtd_phase_meas_vhd \
work/dmtd_with_deglitcher/.dmtd_with_deglitcher_vhd \
work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher_vhd \
work/hpll_period_detect/.hpll_period_detect_vhd \
work/minic_packet_buffer/.minic_packet_buffer_vhd \
work/minic_wb_slave/.minic_wb_slave_vhd \
work/endpoint_pkg/.endpoint_pkg_vhd \
work/softpll_wb/.softpll_wb_vhd \
work/wr_softpll/.wr_softpll_vhd \
work/wrc_lm32/.wrc_lm32_vhd \
work/dec_8b10b/.dec_8b10b_vhd \
work/enc_8b10b/.enc_8b10b_vhd \
work/wr_tbi_phy/.wr_tbi_phy_vhd \
work/wr_mini_nic/.wr_mini_nic_vhd \
work/ep_enc_8b10b/.ep_enc_8b10b_vhd \
work/ep_dec_8b10b/.ep_dec_8b10b_vhd \
work/ep_rx_pcs_tbi/.ep_rx_pcs_tbi_vhd \
work/ep_tx_pcs_tbi/.ep_tx_pcs_tbi_vhd \
work/ep_autonegotiation/.ep_autonegotiation_vhd \
work/ep_pcs_tbi_mdio_wb/.ep_pcs_tbi_mdio_wb_vhd \
work/ep_1000basex_pcs/.ep_1000basex_pcs_vhd \
work/ep_rx_crc_size_check/.ep_rx_crc_size_check_vhd \
work/ep_rx_deframer/.ep_rx_deframer_vhd \
work/ep_tx_framer/.ep_tx_framer_vhd \
work/ep_flow_control/.ep_flow_control_vhd \
work/ep_timestamping_unit/.ep_timestamping_unit_vhd \
work/ep_rmon_counters/.ep_rmon_counters_vhd \
work/ep_rx_buffer/.ep_rx_buffer_vhd \
work/ep_sync_detect/.ep_sync_detect_vhd \
work/ep_wishbone_controller/.ep_wishbone_controller_vhd \
work/ep_ts_counter/.ep_ts_counter_vhd \
work/wrsw_endpoint/.wrsw_endpoint_vhd \
work/pps_gen_wb/.pps_gen_wb_vhd \
work/wrsw_pps_gen/.wrsw_pps_gen_vhd \
work/wbconmax_pkg/.wbconmax_pkg_vhd \
work/wrc_dpram/.wrc_dpram_vhd \
work/wrcore_pkg/.wrcore_pkg_vhd \
work/wrc_periph/.wrc_periph_vhd \
work/wb_reset/.wb_reset_vhd \
work/fd_acam_timestamper/.fd_acam_timestamper_vhd \
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor_vhd \
work/fd_channel_wishbone_slave/.fd_channel_wishbone_slave_vhd \
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit_vhd \
work/fd_delay_channel_driver/.fd_delay_channel_driver_vhd \
work/fd_ring_buffer/.fd_ring_buffer_vhd \
work/fd_dmtd_insertion_calibrator/.fd_dmtd_insertion_calibrator_vhd \
work/fd_dmtd_with_deglitcher/.fd_dmtd_with_deglitcher_vhd \
work/fd_hpll_period_detect/.fd_hpll_period_detect_vhd \
work/fd_reset_generator/.fd_reset_generator_vhd \
work/gc_crc_gen/.gc_crc_gen_vhd \
work/gc_moving_average/.gc_moving_average_vhd \
work/gc_extend_pulse/.gc_extend_pulse_vhd \
......@@ -250,12 +163,21 @@ work/gc_delay_gen/.gc_delay_gen_vhd \
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd \
work/gc_serial_dac/.gc_serial_dac_vhd \
work/gc_sync_ffs/.gc_sync_ffs_vhd \
work/fd_ring_buffer/.fd_ring_buffer_vhd \
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd \
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd \
work/gc_frequency_meter/.gc_frequency_meter_vhd \
work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd \
work/gc_wfifo/.gc_wfifo_vhd \
work/fd_csync_generator/.fd_csync_generator_vhd \
work/memory_loader_pkg/.memory_loader_pkg_vhd \
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd \
work/fine_delay_core/.fine_delay_core_vhd \
work/generic_async_fifo/.generic_async_fifo_vhd \
work/generic_dpram/.generic_dpram_vhd \
work/generic_spram/.generic_spram_vhd \
work/generic_sync_fifo/.generic_sync_fifo_vhd \
work/wb_async_bridge/.wb_async_bridge_vhd \
work/xwb_async_bridge/.xwb_async_bridge_vhd \
work/wb_onewire_master/.wb_onewire_master_vhd \
work/xwb_onewire_master/.xwb_onewire_master_vhd \
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd \
......@@ -264,42 +186,40 @@ work/i2c_master_top/.i2c_master_top_vhd \
work/wb_i2c_master/.wb_i2c_master_vhd \
work/xwb_i2c_master/.xwb_i2c_master_vhd \
work/xwb_bus_fanout/.xwb_bus_fanout_vhd \
work/wb_conmax_pri_dec/.wb_conmax_pri_dec_vhd \
work/wb_conmax_pri_enc/.wb_conmax_pri_enc_vhd \
work/wb_conmax_arb/.wb_conmax_arb_vhd \
work/wb_conmax_msel/.wb_conmax_msel_vhd \
work/wr_core/.wr_core_vhd \
work/wb_conmax_slave_if/.wb_conmax_slave_if_vhd \
work/wb_conmax_master_if/.wb_conmax_master_if_vhd \
work/wb_conmax_rf/.wb_conmax_rf_vhd \
work/wb_conmax_top/.wb_conmax_top_vhd \
work/xwb_dpram/.xwb_dpram_vhd \
work/wb_gpio_port/.wb_gpio_port_vhd \
work/xwb_gpio_port/.xwb_gpio_port_vhd \
work/wb_tics/.wb_tics_vhd \
work/xwb_tics/.xwb_tics_vhd \
work/uart_async_rx/.uart_async_rx_vhd \
work/uart_async_tx/.uart_async_tx_vhd \
work/uart_baud_gen/.uart_baud_gen_vhd \
work/uart_wb_slave/.uart_wb_slave_vhd \
work/simple_uart_pkg/.simple_uart_pkg_vhd \
work/simple_uart_wb/.simple_uart_wb_vhd \
work/wb_simple_uart/.wb_simple_uart_vhd \
work/xwb_simple_uart/.xwb_simple_uart_vhd \
work/vic_prio_enc/.vic_prio_enc_vhd \
work/wb_slave_vic/.wb_slave_vic_vhd \
work/wb_vic/.wb_vic_vhd \
work/xwb_vic/.xwb_vic_vhd \
work/wb_spi/.wb_spi_vhd \
work/xwb_spi/.xwb_spi_vhd \
work/wb_virtual_uart/.wb_virtual_uart_vhd \
work/wb_virtual_uart_slave/.wb_virtual_uart_slave_vhd \
work/sdwb_rom/.sdwb_rom_vhd \
work/xwb_crossbar/.xwb_crossbar_vhd \
work/xwb_sdwb_crossbar/.xwb_sdwb_crossbar_vhd \
work/xwb_lm32/.xwb_lm32_vhd \
work/wb_slave_adapter/.wb_slave_adapter_vhd \
work/xloader_registers_pkg/.xloader_registers_pkg_vhd \
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd \
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd \
work/xloader_wb/.xloader_wb_vhd \
work/xwb_clock_crossing/.xwb_clock_crossing_vhd \
work/xwb_dma/.xwb_dma_vhd \
work/wbgen2_dpssram/.wbgen2_dpssram_vhd \
work/wbgen2_eic/.wbgen2_eic_vhd \
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd \
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd \
work/fd_wishbone_slave/.fd_wishbone_slave_vhd \
work/gn4124_core/.gn4124_core_vhd \
work/dma_controller/.dma_controller_vhd \
work/l2p_ser/.l2p_ser_vhd \
work/p2l_des/.p2l_des_vhd \
work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff_vhd \
work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se_vhd \
work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff_vhd \
work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se_vhd \
work/fd_main_wishbone_slave/.fd_main_wishbone_slave_vhd \
LIBS := work
LIB_IND := work/.work
......@@ -317,172 +237,156 @@ clean:
work/.work:
(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work
work/main/.main_sv: main.sv ../../include/random_pulse_gen.sv ../../include/jittery_delay.sv ../../include/ideal_timestamper.sv ../../include/acam_model.sv ../../include/mc100ep195.sv ../../include/fine_delay_regs.v ../../include/tunable_clock_gen.sv
work/main/.main_sv: main.sv ../../include/random_pulse_gen.sv ../../include/jittery_delay.sv ../../include/ideal_timestamper.sv ../../include/regs/fd_channel_regs.vh ../../include/acam_model.sv ../../include/mc100ep195.sv ../../include/regs/fd_main_regs.vh ../../include/tunable_clock_gen.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+. +incdir+../../include +incdir+../../include/wb $<
@mkdir -p $(dir $@) && touch $@
work/lm32_cpu/.lm32_cpu_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_cpu.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/lm32_addsub/.lm32_addsub_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_addsub.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
work/sockit_owm/.sockit_owm_v: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master $<
@mkdir -p $(dir $@) && touch $@
work/lm32_top/.lm32_top_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_top.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
work/spi_clgen/.spi_clgen_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/lm32_instruction_unit/.lm32_instruction_unit_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_instruction_unit.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
work/spi_shift/.spi_shift_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/lm32_decoder/.lm32_decoder_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_decoder.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
work/spi_top/.spi_top_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/lm32_load_store_unit/.lm32_load_store_unit_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_load_store_unit.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
work/lm32_allprofiles/.lm32_allprofiles_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated $<
@mkdir -p $(dir $@) && touch $@
work/lm32_adder/.lm32_adder_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_adder.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_logic_op/.lm32_logic_op_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_logic_op.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
work/jtag_cores/.jtag_cores_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_shifter/.lm32_shifter_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_shifter.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
work/lm32_adder/.lm32_adder_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_multiplier/.lm32_multiplier_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_multiplier.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
work/lm32_addsub/.lm32_addsub_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_interrupt/.lm32_interrupt_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_interrupt.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
work/lm32_dp_ram/.lm32_dp_ram_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_dp_ram/.lm32_dp_ram_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_dp_ram.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
work/lm32_logic_op/.lm32_logic_op_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/sockit_owm/.sockit_owm_v: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master $<
work/lm32_ram/.lm32_ram_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/spi_clgen/.spi_clgen_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
work/lm32_shifter/.lm32_shifter_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/spi_shift/.spi_shift_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
work/lm32_multiplier/.lm32_multiplier_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic $<
@mkdir -p $(dir $@) && touch $@
work/spi_top/.spi_top_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
work/jtag_tap/.jtag_tap_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
work/fd_ddr_driver/.fd_ddr_driver_vhd: ../../platform/fd_ddr_driver.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gencores_pkg/.gencores_pkg_vhd: ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
work/fd_ddr_pll/.fd_ddr_pll_vhd: ../../platform/fd_ddr_pll.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/genram_pkg/.genram_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_ts_adder/.fd_ts_adder_vhd: ../../rtl/fd_ts_adder.vhd
work/fd_channel_wbgen2_pkg/.fd_channel_wbgen2_pkg_vhd: ../../rtl/fd_channel_wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_ts_normalizer/.fd_ts_normalizer_vhd: ../../rtl/fd_ts_normalizer.vhd
work/fd_ts_adder/.fd_ts_adder_vhd: ../../rtl/fd_ts_adder.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_wbgen2_pkg/.fd_wbgen2_pkg_vhd: ../../rtl/fd_wbgen2_pkg.vhd
work/genram_pkg/.genram_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_wbgen2_pkg/.fd_wbgen2_pkg: \
work/wbgen2_pkg/.wbgen2_pkg
work/fd_csync_generator/.fd_csync_generator_vhd: ../../rtl/fd_csync_generator.vhd
work/gencores_pkg/.gencores_pkg_vhd: ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_csync_generator/.fd_csync_generator: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/gencores_pkg/.gencores_pkg: \
work/genram_pkg/.genram_pkg
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit_vhd: ../../rtl/fd_timestamper_stat_unit.vhd
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg_vhd: ../../rtl/fd_main_wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg: \
work/wbgen2_pkg/.wbgen2_pkg
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor_vhd: ../../rtl/fd_acam_timestamp_postprocessor.vhd
work/wishbone_pkg/.wishbone_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/wishbone_pkg/.wishbone_pkg: \
work/genram_pkg/.genram_pkg
work/fine_delay_pkg/.fine_delay_pkg_vhd: ../../rtl/fine_delay_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_delay_line_arbiter/.fd_delay_line_arbiter_vhd: ../../rtl/fd_delay_line_arbiter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_rearm_generator/.fd_rearm_generator_vhd: ../../rtl/fd_rearm_generator.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fine_delay_pkg/.fine_delay_pkg: \
work/wishbone_pkg/.wishbone_pkg \
work/fd_channel_wbgen2_pkg/.fd_channel_wbgen2_pkg \
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/fd_reset_generator/.fd_reset_generator_vhd: ../../rtl/fd_reset_generator.vhd
work/fd_delay_line_arbiter/.fd_delay_line_arbiter_vhd: ../../rtl/fd_delay_line_arbiter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_reset_generator/.fd_reset_generator: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/fd_spi_master/.fd_spi_master_vhd: ../../rtl/fd_spi_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -494,710 +398,558 @@ work/fd_spi_dac_arbiter/.fd_spi_dac_arbiter_vhd: ../../rtl/fd_spi_dac_arbiter.vh
work/fd_spi_dac_arbiter/.fd_spi_dac_arbiter: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/fd_delay_channel_driver/.fd_delay_channel_driver_vhd: ../../rtl/fd_delay_channel_driver.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_delay_channel_driver/.fd_delay_channel_driver: \
work/fine_delay_pkg/.fine_delay_pkg
work/wishbone_pkg/.wishbone_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gn4124_core_private_pkg/.gn4124_core_private_pkg_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core_private_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller_wb_slave.vhd
work/fd_acam_timestamper/.fd_acam_timestamper_vhd: ../../rtl/fd_acam_timestamper.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gn4124_core_pkg/.gn4124_core_pkg_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/gn4124_core_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_acam_timestamper/.fd_acam_timestamper: \
work/fine_delay_pkg/.fine_delay_pkg \
work/gencores_pkg/.gencores_pkg \
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/l2p_arbiter/.l2p_arbiter_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/l2p_arbiter.vhd
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor_vhd: ../../rtl/fd_acam_timestamp_postprocessor.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/l2p_arbiter/.l2p_arbiter: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor: \
work/fine_delay_pkg/.fine_delay_pkg \
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/l2p_dma_master/.l2p_dma_master_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/l2p_dma_master.vhd
work/fd_channel_wishbone_slave/.fd_channel_wishbone_slave_vhd: ../../rtl/fd_channel_wishbone_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/l2p_dma_master/.l2p_dma_master: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg \
work/genram_pkg/.genram_pkg
work/fd_channel_wishbone_slave/.fd_channel_wishbone_slave: \
work/fd_channel_wbgen2_pkg/.fd_channel_wbgen2_pkg
work/p2l_decode32/.p2l_decode32_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/p2l_decode32.vhd
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit_vhd: ../../rtl/fd_timestamper_stat_unit.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/p2l_decode32/.p2l_decode32: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit: \
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/p2l_dma_master/.p2l_dma_master_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/p2l_dma_master.vhd
work/fd_delay_channel_driver/.fd_delay_channel_driver_vhd: ../../rtl/fd_delay_channel_driver.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/p2l_dma_master/.p2l_dma_master: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg \
work/genram_pkg/.genram_pkg
work/fd_delay_channel_driver/.fd_delay_channel_driver: \
work/wishbone_pkg/.wishbone_pkg \
work/fine_delay_pkg/.fine_delay_pkg \
work/gencores_pkg/.gencores_pkg \
work/fd_channel_wbgen2_pkg/.fd_channel_wbgen2_pkg
work/wbmaster32/.wbmaster32_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/wbmaster32.vhd
work/fd_ring_buffer/.fd_ring_buffer_vhd: ../../rtl/fd_ring_buffer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbmaster32/.wbmaster32: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg \
work/genram_pkg/.genram_pkg
work/gtp_bitslide/.gtp_bitslide_vhd: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_ring_buffer/.fd_ring_buffer: \
work/fine_delay_pkg/.fine_delay_pkg \
work/genram_pkg/.genram_pkg \
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/gtp_phase_align/.gtp_phase_align_vhd: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
work/fd_dmtd_insertion_calibrator/.fd_dmtd_insertion_calibrator_vhd: ../../rtl/fd_dmtd_insertion_calibrator.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/whiterabbitgtp_wrapper_tile/.whiterabbitgtp_wrapper_tile_vhd: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_dmtd_insertion_calibrator/.fd_dmtd_insertion_calibrator: \
work/wishbone_pkg/.wishbone_pkg \
work/fine_delay_pkg/.fine_delay_pkg \
work/genram_pkg/.genram_pkg \
work/gencores_pkg/.gencores_pkg \
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6_vhd: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
work/fd_dmtd_with_deglitcher/.fd_dmtd_with_deglitcher_vhd: ../../rtl/timing/fd_dmtd_with_deglitcher.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6: \
work/fd_dmtd_with_deglitcher/.fd_dmtd_with_deglitcher: \
work/gencores_pkg/.gencores_pkg
work/dmtd_phase_meas/.dmtd_phase_meas_vhd: ../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd
work/fd_hpll_period_detect/.fd_hpll_period_detect_vhd: ../../rtl/timing/fd_hpll_period_detect.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/dmtd_phase_meas/.dmtd_phase_meas: \
work/fd_hpll_period_detect/.fd_hpll_period_detect: \
work/gencores_pkg/.gencores_pkg
work/dmtd_with_deglitcher/.dmtd_with_deglitcher_vhd: ../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd
work/fd_reset_generator/.fd_reset_generator_vhd: ../../rtl/fd_reset_generator.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/dmtd_with_deglitcher/.dmtd_with_deglitcher: \
work/gencores_pkg/.gencores_pkg
work/fd_reset_generator/.fd_reset_generator: \
work/gencores_pkg/.gencores_pkg \
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher_vhd: ../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd
work/gc_crc_gen/.gc_crc_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher: \
work/gc_crc_gen/.gc_crc_gen: \
work/gencores_pkg/.gencores_pkg
work/hpll_period_detect/.hpll_period_detect_vhd: ../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd
work/gc_moving_average/.gc_moving_average_vhd: ../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/hpll_period_detect/.hpll_period_detect: \
work/gc_moving_average/.gc_moving_average: \
work/gencores_pkg/.gencores_pkg
work/minic_packet_buffer/.minic_packet_buffer_vhd: ../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/minic_packet_buffer/.minic_packet_buffer: \
work/genram_pkg/.genram_pkg
work/minic_wb_slave/.minic_wb_slave_vhd: ../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/minic_wb_slave/.minic_wb_slave: \
work/wbgen2_pkg/.wbgen2_pkg
work/endpoint_pkg/.endpoint_pkg_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/endpoint_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/softpll_wb/.softpll_wb_vhd: ../../ip_cores/wr-cores/modules/wr_softpll/softpll_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/softpll_wb/.softpll_wb: \
work/wbgen2_pkg/.wbgen2_pkg
work/wr_softpll/.wr_softpll_vhd: ../../ip_cores/wr-cores/modules/wr_softpll/wr_softpll.vhd
work/gc_extend_pulse/.gc_extend_pulse_vhd: ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_softpll/.wr_softpll: \
work/gc_extend_pulse/.gc_extend_pulse: \
work/gencores_pkg/.gencores_pkg
work/wrc_lm32/.wrc_lm32_vhd: ../../ip_cores/wr-cores/modules/wrc_lm32/wrc_lm32.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/dec_8b10b/.dec_8b10b_vhd: ../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/enc_8b10b/.enc_8b10b_vhd: ../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_tbi_phy/.wr_tbi_phy_vhd: ../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd
work/gc_delay_gen/.gc_delay_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_tbi_phy/.wr_tbi_phy: \
work/gc_delay_gen/.gc_delay_gen: \
work/gencores_pkg/.gencores_pkg
work/wr_mini_nic/.wr_mini_nic_vhd: ../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd: ../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_mini_nic/.wr_mini_nic: \
work/endpoint_pkg/.endpoint_pkg
work/gc_dual_pi_controller/.gc_dual_pi_controller: \
work/gencores_pkg/.gencores_pkg
work/ep_enc_8b10b/.ep_enc_8b10b_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_enc_8b10b.vhd
work/gc_serial_dac/.gc_serial_dac_vhd: ../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_dec_8b10b/.ep_dec_8b10b_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_dec_8b10b.vhd
work/gc_sync_ffs/.gc_sync_ffs_vhd: ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_rx_pcs_tbi/.ep_rx_pcs_tbi_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_pcs_tbi.vhd
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd: ../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_rx_pcs_tbi/.ep_rx_pcs_tbi: \
work/endpoint_pkg/.endpoint_pkg \
work/gc_arbitrated_mux/.gc_arbitrated_mux: \
work/genram_pkg/.genram_pkg \
work/gencores_pkg/.gencores_pkg
work/ep_tx_pcs_tbi/.ep_tx_pcs_tbi_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_pcs_tbi.vhd
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd: ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_tx_pcs_tbi/.ep_tx_pcs_tbi: \
work/endpoint_pkg/.endpoint_pkg \
work/genram_pkg/.genram_pkg \
work/gc_pulse_synchronizer/.gc_pulse_synchronizer: \
work/gencores_pkg/.gencores_pkg
work/ep_autonegotiation/.ep_autonegotiation_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_autonegotiation.vhd
work/gc_frequency_meter/.gc_frequency_meter_vhd: ../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_autonegotiation/.ep_autonegotiation: \
work/endpoint_pkg/.endpoint_pkg
work/gc_frequency_meter/.gc_frequency_meter: \
work/gencores_pkg/.gencores_pkg
work/ep_pcs_tbi_mdio_wb/.ep_pcs_tbi_mdio_wb_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_pcs_tbi_mdio_wb.vhd
work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd: ../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_1000basex_pcs/.ep_1000basex_pcs_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_1000basex_pcs.vhd
work/gc_wfifo/.gc_wfifo_vhd: ../../ip_cores/general-cores/modules/common/gc_wfifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_1000basex_pcs/.ep_1000basex_pcs: \
work/endpoint_pkg/.endpoint_pkg
work/ep_rx_crc_size_check/.ep_rx_crc_size_check_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_crc_size_check.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_rx_crc_size_check/.ep_rx_crc_size_check: \
work/endpoint_pkg/.endpoint_pkg \
work/gc_wfifo/.gc_wfifo: \
work/gencores_pkg/.gencores_pkg
work/ep_rx_deframer/.ep_rx_deframer_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_deframer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_rx_deframer/.ep_rx_deframer: \
work/endpoint_pkg/.endpoint_pkg
work/ep_tx_framer/.ep_tx_framer_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_framer.vhd
work/fd_csync_generator/.fd_csync_generator_vhd: ../../rtl/fd_csync_generator.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_tx_framer/.ep_tx_framer: \
work/endpoint_pkg/.endpoint_pkg \
work/gencores_pkg/.gencores_pkg
work/fd_csync_generator/.fd_csync_generator: \
work/fine_delay_pkg/.fine_delay_pkg \
work/genram_pkg/.genram_pkg \
work/gencores_pkg/.gencores_pkg \
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/ep_flow_control/.ep_flow_control_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_flow_control.vhd
work/memory_loader_pkg/.memory_loader_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_flow_control/.ep_flow_control: \
work/endpoint_pkg/.endpoint_pkg
work/memory_loader_pkg/.memory_loader_pkg: \
work/genram_pkg/.genram_pkg
work/ep_timestamping_unit/.ep_timestamping_unit_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_timestamping_unit.vhd
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_timestamping_unit/.ep_timestamping_unit: \
work/endpoint_pkg/.endpoint_pkg \
work/gencores_pkg/.gencores_pkg
work/generic_shiftreg_fifo/.generic_shiftreg_fifo: \
work/genram_pkg/.genram_pkg
work/ep_rmon_counters/.ep_rmon_counters_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rmon_counters.vhd
work/fine_delay_core/.fine_delay_core_vhd: ../../rtl/fine_delay_core.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_rmon_counters/.ep_rmon_counters: \
work/endpoint_pkg/.endpoint_pkg
work/fine_delay_core/.fine_delay_core: \
work/wishbone_pkg/.wishbone_pkg \
work/fine_delay_pkg/.fine_delay_pkg \
work/gencores_pkg/.gencores_pkg \
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/ep_rx_buffer/.ep_rx_buffer_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_buffer.vhd
work/generic_async_fifo/.generic_async_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_rx_buffer/.ep_rx_buffer: \
work/endpoint_pkg/.endpoint_pkg \
work/generic_async_fifo/.generic_async_fifo: \
work/genram_pkg/.genram_pkg
work/ep_sync_detect/.ep_sync_detect_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_sync_detect.vhd
work/generic_dpram/.generic_dpram_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_sync_detect/.ep_sync_detect: \
work/endpoint_pkg/.endpoint_pkg
work/generic_dpram/.generic_dpram: \
work/memory_loader_pkg/.memory_loader_pkg \
work/genram_pkg/.genram_pkg
work/ep_wishbone_controller/.ep_wishbone_controller_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_wishbone_controller.vhd
work/generic_spram/.generic_spram_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_wishbone_controller/.ep_wishbone_controller: \
work/wbgen2_pkg/.wbgen2_pkg
work/generic_spram/.generic_spram: \
work/genram_pkg/.genram_pkg
work/ep_ts_counter/.ep_ts_counter_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_ts_counter.vhd
work/generic_sync_fifo/.generic_sync_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_ts_counter/.ep_ts_counter: \
work/endpoint_pkg/.endpoint_pkg
work/generic_sync_fifo/.generic_sync_fifo: \
work/genram_pkg/.genram_pkg
work/wrsw_endpoint/.wrsw_endpoint_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/wrsw_endpoint.vhd
work/wb_async_bridge/.wb_async_bridge_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrsw_endpoint/.wrsw_endpoint: \
work/endpoint_pkg/.endpoint_pkg \
work/wb_async_bridge/.wb_async_bridge: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/pps_gen_wb/.pps_gen_wb_vhd: ../../ip_cores/wr-cores/modules/wrsw_pps_gen/pps_gen_wb.vhd
work/xwb_async_bridge/.xwb_async_bridge_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrsw_pps_gen/.wrsw_pps_gen_vhd: ../../ip_cores/wr-cores/modules/wrsw_pps_gen/wrsw_pps_gen.vhd
work/xwb_async_bridge/.xwb_async_bridge: \
work/wishbone_pkg/.wishbone_pkg
work/wb_onewire_master/.wb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrsw_pps_gen/.wrsw_pps_gen: \
work/wb_onewire_master/.wb_onewire_master: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/wbconmax_pkg/.wbconmax_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrc_dpram/.wrc_dpram_vhd: ../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd
work/xwb_onewire_master/.xwb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrc_dpram/.wrc_dpram: \
work/genram_pkg/.genram_pkg
work/xwb_onewire_master/.xwb_onewire_master: \
work/wishbone_pkg/.wishbone_pkg
work/wrcore_pkg/.wrcore_pkg_vhd: ../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrcore_pkg/.wrcore_pkg: \
work/genram_pkg/.genram_pkg \
work/wbconmax_pkg/.wbconmax_pkg
work/wrc_periph/.wrc_periph_vhd: ../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrc_periph/.wrc_periph: \
work/wrcore_pkg/.wrcore_pkg
work/wb_reset/.wb_reset_vhd: ../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd
work/i2c_master_top/.i2c_master_top_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_acam_timestamper/.fd_acam_timestamper_vhd: ../../rtl/fd_acam_timestamper.vhd
work/wb_i2c_master/.wb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_acam_timestamper/.fd_acam_timestamper: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg \
work/gencores_pkg/.gencores_pkg
work/wb_i2c_master/.wb_i2c_master: \
work/wishbone_pkg/.wishbone_pkg
work/gc_crc_gen/.gc_crc_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
work/xwb_i2c_master/.xwb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_crc_gen/.gc_crc_gen: \
work/gencores_pkg/.gencores_pkg
work/xwb_i2c_master/.xwb_i2c_master: \
work/wishbone_pkg/.wishbone_pkg
work/gc_moving_average/.gc_moving_average_vhd: ../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
work/xwb_bus_fanout/.xwb_bus_fanout_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_moving_average/.gc_moving_average: \
work/gencores_pkg/.gencores_pkg
work/xwb_bus_fanout/.xwb_bus_fanout: \
work/wishbone_pkg/.wishbone_pkg
work/gc_extend_pulse/.gc_extend_pulse_vhd: ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
work/xwb_dpram/.xwb_dpram_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_extend_pulse/.gc_extend_pulse: \
work/gencores_pkg/.gencores_pkg
work/xwb_dpram/.xwb_dpram: \
work/wishbone_pkg/.wishbone_pkg \
work/genram_pkg/.genram_pkg
work/gc_delay_gen/.gc_delay_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
work/wb_gpio_port/.wb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_delay_gen/.gc_delay_gen: \
work/wb_gpio_port/.wb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd: ../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
work/xwb_gpio_port/.xwb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_dual_pi_controller/.gc_dual_pi_controller: \
work/gencores_pkg/.gencores_pkg
work/xwb_gpio_port/.xwb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg
work/gc_serial_dac/.gc_serial_dac_vhd: ../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
work/wb_tics/.wb_tics_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_sync_ffs/.gc_sync_ffs_vhd: ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_tics/.wb_tics: \
work/wishbone_pkg/.wishbone_pkg
work/fd_ring_buffer/.fd_ring_buffer_vhd: ../../rtl/fd_ring_buffer.vhd
work/xwb_tics/.xwb_tics_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_ring_buffer/.fd_ring_buffer: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg \
work/genram_pkg/.genram_pkg
work/xwb_tics/.xwb_tics: \
work/wishbone_pkg/.wishbone_pkg
work/fine_delay_core/.fine_delay_core_vhd: ../../rtl/fine_delay_core.vhd
work/uart_async_rx/.uart_async_rx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fine_delay_core/.fine_delay_core: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/generic_async_fifo/.generic_async_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd
work/uart_async_tx/.uart_async_tx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_async_fifo/.generic_async_fifo: \
work/genram_pkg/.genram_pkg
work/generic_dpram/.generic_dpram_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd
work/uart_baud_gen/.uart_baud_gen_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_dpram/.generic_dpram: \
work/genram_pkg/.genram_pkg
work/generic_spram/.generic_spram_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd
work/simple_uart_pkg/.simple_uart_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_spram/.generic_spram: \
work/genram_pkg/.genram_pkg
work/generic_sync_fifo/.generic_sync_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd
work/simple_uart_wb/.simple_uart_wb_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_sync_fifo/.generic_sync_fifo: \
work/genram_pkg/.genram_pkg
work/simple_uart_wb/.simple_uart_wb: \
work/simple_uart_pkg/.simple_uart_pkg
work/wb_onewire_master/.wb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
work/wb_simple_uart/.wb_simple_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_onewire_master/.wb_onewire_master: \
work/gencores_pkg/.gencores_pkg
work/wb_simple_uart/.wb_simple_uart: \
work/wishbone_pkg/.wishbone_pkg \
work/genram_pkg/.genram_pkg \
work/simple_uart_pkg/.simple_uart_pkg
work/xwb_onewire_master/.xwb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
work/xwb_simple_uart/.xwb_simple_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_onewire_master/.xwb_onewire_master: \
work/xwb_simple_uart/.xwb_simple_uart: \
work/wishbone_pkg/.wishbone_pkg
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
work/vic_prio_enc/.vic_prio_enc_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
work/wb_slave_vic/.wb_slave_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/i2c_master_top/.i2c_master_top_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_slave_vic/.wb_slave_vic: \
work/wbgen2_pkg/.wbgen2_pkg
work/wb_i2c_master/.wb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
work/wb_vic/.wb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_i2c_master/.wb_i2c_master: \
work/wb_vic/.wb_vic: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_i2c_master/.xwb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
work/xwb_vic/.xwb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_i2c_master/.xwb_i2c_master: \
work/xwb_vic/.xwb_vic: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_bus_fanout/.xwb_bus_fanout_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
work/wb_spi/.wb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_bus_fanout/.xwb_bus_fanout: \
work/wb_spi/.wb_spi: \
work/wishbone_pkg/.wishbone_pkg
work/wb_conmax_pri_dec/.wb_conmax_pri_dec_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_pri_enc/.wb_conmax_pri_enc_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_arb/.wb_conmax_arb_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_msel/.wb_conmax_msel_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_core/.wr_core_vhd: ../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_core/.wr_core: \
work/genram_pkg/.genram_pkg \
work/wbconmax_pkg/.wbconmax_pkg \
work/wrcore_pkg/.wrcore_pkg
work/wb_conmax_slave_if/.wb_conmax_slave_if_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd
work/xwb_spi/.xwb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_slave_if/.wb_conmax_slave_if: \
work/wbconmax_pkg/.wbconmax_pkg
work/xwb_spi/.xwb_spi: \
work/wishbone_pkg/.wishbone_pkg
work/wb_conmax_master_if/.wb_conmax_master_if_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd
work/sdwb_rom/.sdwb_rom_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdwb_rom.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_master_if/.wb_conmax_master_if: \
work/wbconmax_pkg/.wbconmax_pkg
work/sdwb_rom/.sdwb_rom: \
work/wishbone_pkg/.wishbone_pkg
work/wb_conmax_rf/.wb_conmax_rf_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd
work/xwb_crossbar/.xwb_crossbar_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_rf/.wb_conmax_rf: \
work/wbconmax_pkg/.wbconmax_pkg
work/xwb_crossbar/.xwb_crossbar: \
work/wishbone_pkg/.wishbone_pkg
work/wb_conmax_top/.wb_conmax_top_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd
work/xwb_sdwb_crossbar/.xwb_sdwb_crossbar_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdwb_crossbar.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_top/.wb_conmax_top: \
work/wbconmax_pkg/.wbconmax_pkg
work/xwb_sdwb_crossbar/.xwb_sdwb_crossbar: \
work/wishbone_pkg/.wishbone_pkg
work/wb_gpio_port/.wb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
work/xwb_lm32/.xwb_lm32_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_gpio_port/.wb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/xwb_lm32/.xwb_lm32: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_gpio_port/.xwb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
work/wb_slave_adapter/.wb_slave_adapter_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_gpio_port/.xwb_gpio_port: \
work/wb_slave_adapter/.wb_slave_adapter: \
work/wishbone_pkg/.wishbone_pkg
work/wb_tics/.wb_tics_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_async_rx/.uart_async_rx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
work/xloader_registers_pkg/.xloader_registers_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_async_tx/.uart_async_tx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xloader_registers_pkg/.xloader_registers_pkg: \
work/wbgen2_pkg/.wbgen2_pkg
work/uart_baud_gen/.uart_baud_gen_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_wb_slave/.uart_wb_slave_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader: \
work/wishbone_pkg/.wishbone_pkg
work/wb_simple_uart/.wb_simple_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/vic_prio_enc/.vic_prio_enc_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg \
work/xloader_registers_pkg/.xloader_registers_pkg
work/wb_vic/.wb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
work/xloader_wb/.xloader_wb_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_vic/.wb_vic: \
work/wishbone_pkg/.wishbone_pkg
work/xloader_wb/.xloader_wb: \
work/wbgen2_pkg/.wbgen2_pkg \
work/xloader_registers_pkg/.xloader_registers_pkg
work/wb_spi/.wb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
work/xwb_clock_crossing/.xwb_clock_crossing_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_spi/.wb_spi: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_clock_crossing/.xwb_clock_crossing: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/xwb_spi/.xwb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
work/xwb_dma/.xwb_dma_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_spi/.xwb_spi: \
work/xwb_dma/.xwb_dma: \
work/wishbone_pkg/.wishbone_pkg
work/wb_virtual_uart/.wb_virtual_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_virtual_uart_slave/.wb_virtual_uart_slave_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_virtual_uart_slave/.wb_virtual_uart_slave: \
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_dpssram/.wbgen2_dpssram_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -1231,64 +983,12 @@ work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../../ip_cores/general-cores/module
work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
work/wbgen2_pkg/.wbgen2_pkg
work/fd_wishbone_slave/.fd_wishbone_slave_vhd: ../../rtl/fd_wishbone_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_wishbone_slave/.fd_wishbone_slave: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg \
work/wbgen2_pkg/.wbgen2_pkg
work/gn4124_core/.gn4124_core_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core.vhd
work/fd_main_wishbone_slave/.fd_main_wishbone_slave_vhd: ../../rtl/fd_main_wishbone_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gn4124_core/.gn4124_core: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/dma_controller/.dma_controller_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/dma_controller/.dma_controller: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/l2p_ser/.l2p_ser_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/l2p_ser.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/l2p_ser/.l2p_ser: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/p2l_des/.p2l_des_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/p2l_des.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/p2l_des/.p2l_des: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_se.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_main_wishbone_slave/.fd_main_wishbone_slave: \
work/wbgen2_pkg/.wbgen2_pkg \
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
hdl/testbench/top/Manifest.py
View file @ c00e32c0
......@@ -3,4 +3,4 @@ action = "simulation"
vlog_opt="+incdir+../../include +incdir+../../include/wb"
files = "main.sv"
modules = {"local": [ "../../rtl" ] }
modules = {"local": [ "../../" ] }
hdl/testbench/top/main.sv
View file @ c00e32c0
......@@ -4,23 +4,34 @@
`include "tunable_clock_gen.sv"
`include "random_pulse_gen.sv"
`include "jittery_delay.sv"
`include "fine_delay_regs.v"
`include "ideal_timestamper.sv"
`include "mc100ep195.sv"
`include "simdrv_defs.svh"
`include "regs/fd_main_regs.vh"
`include "regs/fd_channel_regs.vh"
`include "wb/simdrv_defs.svh"
`include "wb/if_wb_master.svh"
`timescale 10fs/10fs
interface IAcamDirect;
logic [3:0] addr;
endinterface // IAcamDirect
typedef virtual IAcamDirect VIAcamDirect;
module clock_reset_gen
(
output clk_sys_o,
output clk_ref_o,
output clk_tdc_o,
output clk_sys_o,
output clk_ref_o,
output clk_tdc_o,
output clk_dmtd_o,
output reg rst_n_o);
parameter real g_ref_period = 8ns;
parameter real g_dmtd_period = 8.31ns;
parameter real g_sys_period = 16.31ns;
parameter real g_ref_jitter = 10ps;
parameter real g_tdc_jitter = 10ps;
......@@ -62,6 +73,18 @@ module clock_reset_gen
.clk_o(clk_sys_buf)
);
tunable_clock_gen
#(
.g_period(g_dmtd_period),
.g_jitter(0.01)
)
GEN_DMTD
(
.enable_i(enable),
.clk_o(clk_dmtd_o)
);
assign clk_sys_o = clk_sys_buf;
initial begin
......@@ -79,7 +102,7 @@ const int SPI_DAC = 2;
class CSimDrv_FineDelay;
protected CBusAccessor m_acc;
protected VIAcamDirect m_acam;
protected Timestamp ts_queue[$];
const real c_acam_bin = 27.012; // [ps]
......@@ -90,39 +113,79 @@ class CSimDrv_FineDelay;
const int c_acam_merge_c_threshold = 1;
const int c_acam_merge_f_threshold = 2000;
function new(CBusAccessor acc);
function new(CBusAccessor acc, input VIAcamDirect _acam);
m_acc = acc;
m_acam = _acam;
endfunction // new
task acam_write(int addr, int value);
m_acc.write(`ADDR_FD_TAR, (addr<<28) | value);
m_acam.addr = addr;
#10ns;
m_acc.write(`ADDR_FD_TDR, value);
m_acc.write(`ADDR_FD_TDCSR, `FD_TDCSR_WRITE);
endtask // acam_write
task acam_read(int addr, output int value);
uint64_t rval;
m_acc.write(`ADDR_FD_TAR, (addr<<28));
m_acam.addr = addr;
#10ns;
m_acc.write(`ADDR_FD_TDR, (addr<<28));
m_acc.write(`ADDR_FD_TDCSR, `FD_TDCSR_READ);
#(500ns);
m_acc.read(`ADDR_FD_TAR, rval);
m_acc.read(`ADDR_FD_TDR, rval);
value = rval;
endtask // acam_read
task get_time(ref Timestamp t);
uint64_t tcr, secl, sech, cycles;
m_acc.read(`ADDR_FD_TCR, tcr);
m_acc.write(`ADDR_FD_TCR, tcr | `FD_TCR_CAP_TIME);
m_acc.read(`ADDR_FD_TM_SECL, secl);
m_acc.read(`ADDR_FD_TM_SECH, sech);
m_acc.read(`ADDR_FD_TM_CYCLES, cycles);
t.utc = (sech << 32) | secl;
t.coarse = cycles;
t.frac = 0;
endtask // get_time
task csync_int();
m_acc.write(`ADDR_FD_GCR, `FD_GCR_CSYNC_INT);
endtask // csync_int
task set_time(Timestamp t);
uint64_t tcr;
m_acc.read(`ADDR_FD_TCR, tcr);
m_acc.write(`ADDR_FD_TM_SECL, t.utc & 32'hffffffff);
m_acc.write(`ADDR_FD_TM_SECH, t.utc >> 32);
m_acc.write(`ADDR_FD_TM_CYCLES, t.coarse);
m_acc.write(`ADDR_FD_TCR, tcr | `FD_TCR_SET_TIME);
endtask // set_time
task csync_wr();
m_acc.write(`ADDR_FD_GCR, `FD_GCR_CSYNC_WR);
endtask // csync_wr
task set_reference(int wr);
if(wr)
begin
uint64_t rval;
$display("Enabling White Rabbit time reference...");
m_acc.write(`ADDR_FD_TCR, `FD_TCR_WR_ENABLE);
forever begin
m_acc.read(`ADDR_FD_TCR, rval);
if(rval & `FD_TCR_WR_LOCKED) break;
end
$display("WR Locked");
end
else begin
Timestamp t = new(0,0,0);
set_time(t);
end
endtask // set_reference
task rbuf_update();
Timestamp ts;
uint64_t utc, coarse, seq_frac, stat;
uint64_t utc, coarse, seq_frac, stat, sech, secl;
m_acc.read(`ADDR_FD_TSBCR, stat);
......@@ -130,16 +193,18 @@ class CSimDrv_FineDelay;
if((stat & `FD_TSBCR_EMPTY) == 0) begin
m_acc.read(`ADDR_FD_TSBR_U, utc);
m_acc.read(`ADDR_FD_TSBR_C, coarse);
m_acc.read(`ADDR_FD_TSBR_FID, seq_frac);
m_acc.read(`ADDR_FD_TSBR_SECH, sech);
m_acc.read(`ADDR_FD_TSBR_SECL, secl);
m_acc.read(`ADDR_FD_TSBR_CYCLES, coarse);
m_acc.read(`ADDR_FD_TSBR_FID, seq_frac);
ts = new (0,0,0);
ts.utc = utc;
ts.source = seq_frac & 'h7;
ts.utc = (sech << 32) | secl;
ts.coarse = coarse & 'hfffffff;
ts.seq_id = (seq_frac >> 16) & 'hffff;
ts.frac = seq_frac & 'hfff;
ts.frac = (seq_frac>>4) & 'hfff;
ts_queue.push_back(ts);
end
......@@ -154,28 +219,60 @@ class CSimDrv_FineDelay;
endfunction // get
typedef enum
{
DELAY = 0,
PULSE_GEN = 1
} channel_mode_t;
task config_output(int channel, int polarity, int delay_ps, int duration_ps);
uint64_t dcr;
Timestamp t_start, t_end;
task config_output( int channel,channel_mode_t mode, int enable, Timestamp start_delay, uint64_t width_ps, uint64_t delta_ps=0, int rep_count=1);
uint64_t dcr, base, rep;
Timestamp t_start, t_end, t_delta, t_width;
t_width = new;
t_width.unflatten(int'(real'(width_ps) * 4096.0 / 8000.0));
t_start = start_delay;
t_end = start_delay.add(t_width);
t_delta = new;
t_delta.unflatten(int'(real'(delta_ps) * 4096.0 / 8000.0));
base = 'h100 + 'h100 * channel;
m_acc.write(base + `ADDR_FD_FRR, 800);
m_acc.write(base + `ADDR_FD_U_STARTH, t_start.utc >> 32);
m_acc.write(base + `ADDR_FD_U_STARTL, t_start.utc & 'hffffffff);
m_acc.write(base + `ADDR_FD_C_START, t_start.coarse);
m_acc.write(base + `ADDR_FD_F_START, t_start.frac);
m_acc.write(base + `ADDR_FD_U_ENDH, t_end.utc >> 32);
m_acc.write(base + `ADDR_FD_U_ENDL, t_end.utc & 'hffffffff);
m_acc.write(base + `ADDR_FD_C_END, t_end.coarse);
m_acc.write(base + `ADDR_FD_F_END, t_end.frac);
m_acc.write(base + `ADDR_FD_U_DELTA, t_delta.utc & 'hf);
m_acc.write(base + `ADDR_FD_C_DELTA, t_delta.coarse);
m_acc.write(base + `ADDR_FD_F_DELTA, t_delta.frac);
if(rep_count < 0)
rep = `FD_RCR_CONT;
else
rep = (rep_count-1) << `FD_RCR_REP_CNT_OFFSET;
m_acc.write(base + `ADDR_FD_RCR, rep);
dcr = (enable? `FD_DCR_ENABLE : 0) | `FD_DCR_UPDATE ;
if(mode == PULSE_GEN)
dcr |= `FD_DCR_MODE;
if((width_ps < 200000) || (((delta_ps-width_ps) < 150000) && (rep_count > 1)))
begin
dcr |= `FD_DCR_NO_FINE;
$display("NoFine!");
end
t_start = new;
t_start.unflatten(int'(real'(delay_ps) * 4096.0 / 8000.0));
t_end = new;
t_end.unflatten(int'(real'(delay_ps + duration_ps) * 4096.0 / 8000.0));
m_acc.write('h20 * channel + `ADDR_FD_FRR1, 800);
m_acc.write('h20 * channel + `ADDR_FD_U_START1, t_start.utc);
m_acc.write('h20 * channel + `ADDR_FD_C_START1, t_start.coarse);
m_acc.write('h20 * channel + `ADDR_FD_F_START1, t_start.frac);
m_acc.write('h20 * channel + `ADDR_FD_U_END1, t_end.utc);
m_acc.write('h20 * channel + `ADDR_FD_C_END1, t_end.coarse);
m_acc.write('h20 * channel + `ADDR_FD_F_END1, t_end.frac);
dcr = `FD_DCR1_ENABLE | `FD_DCR1_UPDATE | (polarity ? `FD_DCR1_POL : 0);
m_acc.write('h20 * channel + `ADDR_FD_DCR1, dcr);
m_acc.write('h100 + 'h100 * channel + `ADDR_FD_DCR, dcr);
if(mode == PULSE_GEN)
m_acc.write('h100 + 'h100 * channel + `ADDR_FD_DCR, dcr | `FD_DCR_PG_ARM);
endtask // config_output
......@@ -183,6 +280,10 @@ class CSimDrv_FineDelay;
task init();
int rval;
Timestamp t = new;
m_acc.write(`ADDR_FD_RSTR, 'hdeadffff); /* Un-reset the card */
m_acc.write(`ADDR_FD_TDCSR, `FD_TDCSR_START_DIS | `FD_TDCSR_STOP_DIS);
m_acc.write(`ADDR_FD_GCR, `FD_GCR_BYPASS);
......@@ -190,11 +291,14 @@ class CSimDrv_FineDelay;
acam_write(5, c_acam_start_offset); // set StartOffset
acam_read(5, rval);
$display("AcamReadback %x", rval);
m_acam.addr= 8; /* permanently select FIFO1 */
// Clear the ring buffer
m_acc.write(`ADDR_FD_TSBCR, `FD_TSBCR_ENABLE | `FD_TSBCR_PURGE | `FD_TSBCR_RST_SEQ);
m_acc.write(`ADDR_FD_TSBCR, `FD_TSBCR_ENABLE | `FD_TSBCR_PURGE | `FD_TSBCR_RST_SEQ | (3 << `FD_TSBCR_CHAN_MASK_OFFSET));
m_acc.write(`ADDR_FD_ADSFR, int' (real'(1<< (c_frac_bits + c_scaler_shift)) * c_acam_bin / c_ref_period));
......@@ -205,9 +309,12 @@ class CSimDrv_FineDelay;
// Enable trigger input
m_acc.write(`ADDR_FD_GCR, 0);
#(200ns);
csync_wr();
#(100ns);
t.utc = 1;
t.coarse = 1000;
set_time(t);
// get_time(t);
// Enable trigger input
m_acc.write(`ADDR_FD_GCR, `FD_GCR_INPUT_EN);
......@@ -216,9 +323,9 @@ class CSimDrv_FineDelay;
endtask // init
task force_cal_pulse(int channel, int delay_setpoint);
m_acc.write(`ADDR_FD_FRR1 + (channel * 'h20), delay_setpoint);
m_acc.write(`ADDR_FD_DCR1 + (channel * 'h20), `FD_DCR1_FORCE_DLY | `FD_DCR1_POL);
m_acc.write(`ADDR_FD_TDCSR, `FD_TDCSR_CAL_PULSE);
m_acc.write(`ADDR_FD_FRR + (channel * 'h20), delay_setpoint);
m_acc.write(`ADDR_FD_DCR + (channel * 'h20), `FD_DCR_FORCE_DLY);
m_acc.write(`ADDR_FD_CALR, `FD_CALR_CAL_PULSE | ((1<<channel) << `FD_CALR_PSEL_OFFSET));
endtask // force_cal_pulse
......@@ -229,14 +336,14 @@ module wr_time_counter
(
input clk_ref_i,
input rst_n_i,
output [31:0] wr_utc_o,
output [39:0] wr_utc_o,
output [27:0] wr_coarse_o,
output reg wr_time_valid_o
);
parameter g_coarse_range = 256;
parameter g_coarse_range = 125000000;
reg [31:0] utc;
reg [39:0] utc;
reg [27:0] coarse;
always@(posedge clk_ref_i)
......@@ -264,7 +371,7 @@ endmodule // wr_time_counter
module main;
wire clk_sys, clk_ref, clk_tdc, rst_n;
wire clk_sys, clk_ref, clk_tdc, clk_dmtd, rst_n;
wire trig_a;
wire trig_cal;
......@@ -282,13 +389,16 @@ module main;
wire trig_a_n_delayed;
wire tdc_start_delayed;
wire [31:0] wr_utc;
wire [39:0] wr_utc;
wire [27:0] wr_coarse;
wire wr_time_valid;
reg [3:0] tdc_start_div = 0;
reg tdc_start = 0;
wire trig_a_muxed;
wire trig_cal_fpga, trig_a_lemo;
reg trig_cal_sel = 1;
always@(posedge clk_ref) begin
tdc_start_div <= tdc_start_div + 1;
......@@ -297,7 +407,7 @@ module main;
IWishboneMaster
#(
.g_addr_width(8),
.g_addr_width(32),
.g_data_width(32)
) wb_master
(
......@@ -311,6 +421,7 @@ module main;
.clk_sys_o(clk_sys),
.clk_ref_o(clk_ref),
.clk_tdc_o(clk_tdc),
.clk_dmtd_o(clk_dmtd),
.rst_n_o(rst_n)
);
......@@ -328,14 +439,14 @@ module main;
random_pulse_gen
#(
.g_pulse_width(2000ns),
.g_min_spacing(4000.111ns),
.g_max_spacing(4000.112ns)
.g_pulse_width(40ns),
.g_min_spacing(100.111ns),
.g_max_spacing(100.112ns)
)
TRIG_GEN
(
.enable_i(1'b1),
.pulse_o(trig_a)
.pulse_o(trig_a_lemo)
);
// assign trig_a = 0;
......@@ -351,12 +462,18 @@ module main;
.rst_n_i(rst_n),
.clk_ref_i(clk_ref),
.enable_i(~acam_stop_dis[1]),
.trig_a_i(trig_a),
.trig_a_i(trig_a_lemo),
.csync_p1_i(wr_time_valid & !wr_time_valid_d0),
.csync_utc_i(wr_utc),
.csync_coarse_i(wr_coarse)
);
IAcamDirect acam_direct();
assign trig_a_muxed = (trig_cal_sel ? trig_a_lemo : trig_cal_fpga);
acam_model
#(
.g_verbose(0)
......@@ -367,14 +484,14 @@ module main;
.WRN(acam_wr_n),
.RDN(acam_rd_n),
.CSN(acam_cs_n),
.CSN(1'b0),
.OEN(acam_rd_n),
.Adr(acam_adr),
.Adr(acam_direct.addr),
.D(acam_data),
.DStart(tdc_start),
.DStop1(trig_a),
.DStop1(trig_a_muxed),
.DStop2(1'b0),
......@@ -403,7 +520,7 @@ module main;
)
DLY_TRIG
(
.in_i(~trig_a),
.in_i(~trig_a_muxed),
.out_o(trig_a_n_delayed)
);
......@@ -421,28 +538,33 @@ module main;
wire [3:0] delay_len, delay_pulse;
wire [9:0] delay_val;
wire [3:0] d_out;
reg dmtd_fb_in, dmtd_fb_out;
wire dmtd_samp;
fine_delay_core
#(
.g_simulation(1),
.g_with_wr_core(0))
DUT (
.clk_ref_i(clk_ref),
.clk_ref_0_i(clk_ref),
.clk_ref_180_i(~clk_ref),
.clk_dmtd_i(clk_dmtd),
.tdc_start_i(tdc_start),
.clk_sys_i(clk_sys),
.rst_n_i (rst_n),
.trig_a_n_i (trig_a_n_delayed),
.trig_cal_o (trig_cal),
.trig_a_i (~trig_a_n_delayed),
.tdc_cal_pulse_o (trig_cal_fpga),
.acam_a_o(acam_adr),
.acam_d_o (tdc_d_o),
.acam_d_i (acam_data),
.acam_d_oen_o (tdc_d_oe),
.acam_err_i (1'b0),
.acam_int_i (1'b0),
.acam_emptyf_i (acam_ef1),
.acam_alutrigger_o (acam_alutrigger),
.acam_cs_n_o (acam_cs_n),
.acam_wr_n_o (acam_wr_n),
.acam_rd_n_o (acam_rd_n),
......@@ -461,17 +583,25 @@ module main;
.delay_val_o (delay_val),
.delay_pulse_o (delay_pulse),
.wr_utc_i(wr_utc),
.wr_coarse_i(wr_coarse),
.wr_time_valid_i(wr_time_valid),
.wb_adr_i (wb_master.master.adr[7:0]),
.wb_dat_i (wb_master.master.dat_o),
.wb_dat_o (wb_master.master.dat_i),
.wb_cyc_i (wb_master.master.cyc),
.wb_stb_i (wb_master.master.stb),
.wb_we_i (wb_master.master.we),
.wb_ack_o (wb_master.master.ack)
.tm_utc_i(wr_utc),
.tm_cycles_i(wr_coarse),
.tm_time_valid_i(wr_time_valid),
.tm_link_up_i(1'b1),
.tm_clk_aux_locked_i(1'b1),
.dmtd_samp_o(dmtd_samp),
.dmtd_fb_in_i(dmtd_fb_in),
.dmtd_fb_out_i(dmtd_fb_out),
.wb_adr_i (wb_master.adr[31:0]),
.wb_dat_i (wb_master.dat_o),
.wb_dat_o (wb_master.dat_i),
.wb_cyc_i (wb_master.cyc),
.wb_stb_i (wb_master.stb),
.wb_we_i (wb_master.we),
.wb_ack_o (wb_master.ack),
.wb_stall_o(wb_master.stall)
);
......@@ -519,6 +649,23 @@ module main;
Timestamp ts_queue[$];
/* DMTD Calibrator */
reg [3:0] dmtd_out_chx;
always@(posedge dmtd_samp)
begin
dmtd_fb_in <= ~trig_a_muxed;
dmtd_out_chx[0] <= ~d_out[0];
dmtd_out_chx[1] <= ~d_out[1];
end
assign dmtd_fb_out = dmtd_out_chx[0] & dmtd_out_chx[1];
always@(posedge clk_ref)
if(DUT.tag_valid)
begin
......@@ -531,27 +678,52 @@ module main;
CWishboneAccessor wb;
initial begin
int rval;
uint64_t rval;
Timestamp t_cur = new;
wait(rst_n != 0);
@(posedge clk_sys);
$display("Initializing FD Testbench!");
wb = wb_master.get_accessor();
fd_drv = new(wb);
wb_master.settings.cyc_on_stall = 1;
wb.set_mode(PIPELINED);
fd_drv = new(wb, VIAcamDirect'(acam_direct));
fd_drv.init();
fd_drv.get_time(t_cur);
//fd_drv.set_reference(0);
$display("GetTime: %d:%d",t_cur.utc, t_cur.coarse);
t_cur.utc= 0 ;
t_cur.frac = 0;
t_cur.coarse = 500/8;
fd_drv.config_output(0, CSimDrv_FineDelay::DELAY, 1, t_cur, 100000, 100000, 3);
// fd_drv.config_output(0,1, 1000000, 200000);
// fd_drv.config_output(1,1, 1100500, 200000);
// fd_drv.config_output(2,1, 1100900, 200000);
// fd_drv.config_output(2,1, 1100900, 200000);
// fd_drv.config_output(3,1, 1110100, 200000);
fd_drv.force_cal_pulse(0, 100);
// fd_drv.force_cal_pulse(0, 100);
// #(320ns);
// fd_drv.force_cal_pulse(0, 200);
forever fd_drv.rbuf_update();
// forever fd_drv.rbuf_update();
end
Timestamp prev = null;
......@@ -578,11 +750,11 @@ module main;
// delta3 = t_out1.flatten() - t_ideal.flatten();
$display("TS: seq %d delta %.4f delta_out %.4f %.4f", t_acam.seq_id, delta, delta2, delta3);
$display("TS: seq %d [%d:%d:%d src %d] delta %.4f delta_out %.4f %.4f", t_acam.seq_id, t_acam.utc, t_acam.coarse, t_acam.frac, t_acam.source, delta, delta2, delta3);
if(delta > 0.1 || delta < -0.1)
begin
$display("TS Failure");
$stop;
// $display("TS Failure");
// $stop;
end
end
end
......
hdl/testbench/top/run.do
View file @ c00e32c0
make
#make
vsim -L XilinxCoreLib work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
do wave.do
run 1us
run 100us
wave zoomfull
\ No newline at end of file
hdl/testbench/top/wave.do
View file @ c00e32c0
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/clk_ref_i
add wave -noupdate /main/DUT/clk_sys_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/trig_a_n_i
add wave -noupdate /main/DUT/trig_cal_o
add wave -noupdate /main/DUT/tdc_start_i
add wave -noupdate /main/DUT/led_trig_o
add wave -noupdate /main/DUT/acam_a_o
add wave -noupdate /main/DUT/acam_d_o
add wave -noupdate /main/DUT/acam_d_i
add wave -noupdate /main/DUT/acam_d_oen_o
add wave -noupdate /main/DUT/acam_err_i
add wave -noupdate /main/DUT/acam_int_i
add wave -noupdate /main/DUT/acam_emptyf_i
add wave -noupdate /main/DUT/acam_alutrigger_o
add wave -noupdate /main/DUT/acam_cs_n_o
add wave -noupdate /main/DUT/acam_wr_n_o
add wave -noupdate /main/DUT/acam_rd_n_o
add wave -noupdate /main/DUT/acam_start_dis_o
add wave -noupdate /main/DUT/acam_stop_dis_o
add wave -noupdate /main/DUT/spi_cs_dac_n_o
add wave -noupdate /main/DUT/spi_cs_pll_n_o
add wave -noupdate /main/DUT/spi_cs_gpio_n_o
add wave -noupdate /main/DUT/spi_sclk_o
add wave -noupdate /main/DUT/spi_mosi_o
add wave -noupdate /main/DUT/spi_miso_i
add wave -noupdate /main/DUT/delay_len_o
add wave -noupdate /main/DUT/delay_val_o
add wave -noupdate /main/DUT/delay_pulse_o
add wave -noupdate /main/DUT/wr_time_valid_i
add wave -noupdate /main/DUT/wr_coarse_i
add wave -noupdate /main/DUT/wr_utc_i
add wave -noupdate /main/DUT/owr_en_o
add wave -noupdate /main/DUT/owr_i
add wave -noupdate /main/DUT/wb_adr_i
add wave -noupdate /main/DUT/wb_dat_i
add wave -noupdate /main/DUT/wb_dat_o
add wave -noupdate /main/DUT/wb_cyc_i
add wave -noupdate /main/DUT/wb_stb_i
add wave -noupdate /main/DUT/wb_we_i
add wave -noupdate /main/DUT/wb_ack_o
add wave -noupdate /main/DUT/wb_irq_o
add wave -noupdate /main/DUT/tag_frac
add wave -noupdate /main/DUT/tag_coarse
add wave -noupdate /main/DUT/tag_utc
add wave -noupdate /main/DUT/tag_valid
add wave -noupdate /main/DUT/rbuf_frac
add wave -noupdate /main/DUT/rbuf_coarse
add wave -noupdate /main/DUT/rbuf_utc
add wave -noupdate /main/DUT/rbuf_valid
add wave -noupdate /main/DUT/master_csync_p1
add wave -noupdate /main/DUT/master_csync_utc
add wave -noupdate /main/DUT/master_csync_coarse
add wave -noupdate /main/DUT/rst_n_sys
add wave -noupdate /main/DUT/rst_n_ref
add wave -noupdate /main/DUT/advance_rbuf
add wave -noupdate /main/DUT/rbuf_irq
add wave -noupdate /main/DUT/tdc_rearm_p1
add wave -noupdate /main/DUT/tdc_start_p1
add wave -noupdate /main/DUT/dcr_enable_vec
add wave -noupdate /main/DUT/dcr_mode_vec
add wave -noupdate /main/DUT/chx_rearm
add wave -noupdate /main/DUT/chx_delay_pulse
add wave -noupdate /main/DUT/chx_delay_value
add wave -noupdate /main/DUT/chx_delay_load
add wave -noupdate /main/DUT/chx_delay_load_done
add wave -noupdate /main/DUT/fan_out
add wave -noupdate /main/DUT/fan_in
add wave -noupdate /main/DUT/wb_in
add wave -noupdate /main/DUT/wb_out
add wave -noupdate /main/DUT/regs_fromwb
add wave -noupdate /main/DUT/regs_towb_csync
add wave -noupdate /main/DUT/regs_towb_tsu
add wave -noupdate /main/DUT/regs_towb_rbuf
add wave -noupdate /main/DUT/regs_towb_local
add wave -noupdate /main/DUT/regs_towb
add wave -noupdate /main/DUT/spi_cs_vec
add wave -noupdate /main/DUT/owr_en_int
add wave -noupdate /main/DUT/owr_int
add wave -noupdate /main/DUT/dbg
add wave -noupdate /main/DUT/gen_cal_pulse
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_with_internal_timebase
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_clk_sys_freq
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_counter_bits
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/clk_sys_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/clk_in_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/rst_n_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/pps_p1_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_o
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_valid_o
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/gate_pulse
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/gate_pulse_synced
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/cntr_gate
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/cntr_meas
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_reg
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {3716002840 fs} 0}
configure wave -namecolwidth 413
WaveRestoreCursors {{Cursor 1} {8145325200 fs} 0}
configure wave -namecolwidth 183
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -97,4 +30,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {3191002840 fs} {4241002840 fs}
WaveRestoreZoom {0 fs} {26250 ns}
hdl/top/spec/wr/Manifest.py
View file @ c00e32c0
files = ["spec_top.vhd", "spec_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd"]
fetchto = "../../ip_cores"
fetchto = "../../../ip_cores"
modules = {
"local" : ["../../rtl",
"local" : ["../../../rtl",
"../../../../../wr-repos/wr-hdl/modules/mini_bone",
"../../../../../wr-repos/wr-hdl"],
"svn" : [ "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" ]
......
software/include/fdelay_lib.h
View file @ c00e32c0
......@@ -9,11 +9,12 @@
/* fdelay_get_timing_status() return values: */
#define FDELAY_FREE_RUNNING 0x10 /* attached WR core is offline */
#define FDELAY_FREE_RUNNING 0x10 /* local oscillator is free running */
#define FDELAY_WR_OFFLINE 0x8 /* attached WR core is offline */
#define FDELAY_WR_READY 0x1 /* attached WR core is synchronized, we can sync the fine delay core anytime */
#define FDELAY_WR_SYNCING 0x2 /* local oscillator is being synchronized with WR clock */
#define FDELAY_WR_SYNCED 0x4 /* we are synced. */
#define FDELAY_WR_NOT_PRESENT 0x20 /* No WR Core present */
/* fdelay_configure_sync() flags */
......@@ -23,7 +24,7 @@
/* Hardware "handle" structure */
typedef struct fdelay_device
{
/* Base address of the FD core */
/* Base address of the FD core (relative to the beginning of local writel/readl address spaces) */
uint32_t base_addr;
/* Bus-specific readl/writel functions - so the same library can be used both with
......@@ -37,11 +38,10 @@ typedef struct fdelay_device
typedef struct
{
int64_t utc;
int32_t coarse;
int32_t frac;
uint16_t seq_id;
int channel;
int32_t utc; /* TAI seconds */ /* FIXME: replace all UTCs with TAIs or seconds for clarity */
int32_t coarse; /* 125 MHz counter cycles */
int32_t frac; /* Fractional part (<8ns) */
uint16_t seq_id; /* Sequence ID to detect missed timestamps */
} fdelay_time_t;
/*
......@@ -51,24 +51,67 @@ PUBLIC API
*/
fdelay_device_t *fdelay_create_rawrabbit(uint32_t base_addr);
/* Creates a local instance of Fine Delay Core at address base_addr. Returns a non-null fdelay_device_t
card context on success or null if an error occured */
fdelay_device_t *fdelay_create(const char *device);
/* Does the same as above, but for a card accessible via EtherBone/MiniBone.
iface = network interface to which the carrier is connected
mac_addr = MAC address of the EtherBone/MiniBone core
base_addr = base address of the FD core (relative to EB/MB address space) */
fdelay_device_t *fdelay_create_minibone(char *iface, char *mac_addr, uint32_t base_addr);
/* Helper functions - converting FD timestamp format from/to plain picoseconds */
fdelay_time_t fdelay_from_picos(const uint64_t ps);
int64_t fdelay_to_picos(const fdelay_time_t t);
/* Initializes and calibrates the device. 0 = success, negative = error */
int fdelay_init(fdelay_device_t *dev);
/* Disables and releases the resources for a given FD Card */
int fdelay_release(fdelay_device_t *dev);
int fdelay_read(fdelay_device_t *dev, fdelay_time_t *timestamps, int how_many);
/* Returns an explaination of the last error occured on device dev (TBI) */
char *fdelay_strerror(fdelay_device_t *dev);
/* Sets the timing reference for the card (ref source). Currently there are two choices:
- FDELAY_SYNC_LOCAL - use local oscillator
- FDELAY_SYNC_WR - use White Rabbit */
int fdelay_set_timing_reference(fdelay_device_t *dev, int ref_source);
/* Polls the current status of the timing source. Returns a combination of
.... SYNCED flags. wait_mask can enable/disable waiting for a change of
a particular flag or set of flags. For example, calling
fdelay_get_timing_status(dev, FDELAY_WR_SYNCED) will wait until a change of
FDELAY_WR_SYNCED bit. */
int fdelay_get_timing_status(fdelay_device_t *dev, int wait_mask);
/* Configures the trigger input (TDC/Delay modes). enable enables the input,
termination switches on/off the built-in 50 Ohm termination resistor */
int fdelay_configure_trigger(fdelay_device_t *dev, int enable, int termination);
int fdelay_configure_output(fdelay_device_t *dev, int channel, int enable, int64_t delay_ps, int64_t width_ps, int64_t delta_ps, int rep_count);
int fdelay_configure_sync(fdelay_device_t *dev, int mode);
int fdelay_update_sync_status(fdelay_device_t *dev);
int fdelay_set_time(fdelay_device_t *dev, const fdelay_time_t t);
int fdelay_configure_pulse_gen(fdelay_device_t *dev, int channel, int enable, fdelay_time_t t_start, int64_t width_ps, int64_t delta_ps, int rep_count);
int fdelay_channel_triggered(fdelay_device_t *dev, int channel);
int fdelay_get_time(fdelay_device_t *dev, fdelay_time_t *t);
/* Configures timestamp buffer capture: enable = TS buffer enabled, channel mask:
channels to time tag (bit 0 = TDC, bits 1..4 = outputs 1..4) */
int fdelay_configure_capture (fdelay_device_t *dev, int enable, int channel_mask);
/* Reads how_many timestamps from the buffer. Blocking */
/* TODO: non-blocking version? */
int fdelay_read (fdelay_device_t *dev, fdelay_time_t *timestamps, int how_many);
/* (delay mode only) Configures output(s) selected in channel_mask to work in delay mode. Delta_ps = spacing between
the rising edges of subsequent pulses. */
int fdelay_configure_delay (fdelay_device_t *dev, int channel_mask, int enable, int64_t delay_ps, int64_t width_ps, int64_t delta_ps, int repeat_count);
/* (pulse mode only) Configures output(s) selected in channel_mask to produce pulse(s) starting at (start) with appropriate width/spacing/repeat_count */
int fdelay_configure_pulse_gen(fdelay_device_t *dev, int channel_mask, int enable, fdelay_time_t start, int64_t width_ps, int64_t delta_ps, int repeat_count);
/* (pulse mode only) Returns non-0 when all of the channels in channel mask have produced their programmed pulses */
int fdelay_outputs_triggered(fdelay_device_t *dev, int channel_mask, int blocking);
#endif
software/lib/fdelay_lib.c
View file @ c00e32c0
......@@ -883,7 +883,7 @@ int fdelay_init(fdelay_device_t *dev)
if(ds18x_init(dev) < 0)
{
fail(TEST_SPI, "DS18x sensor not detected.");
fail(TEST_SPI, "DS18x sensor not detected.");
dbg("DS18x sensor not detected. Bah!\n");
return -1;
}
......@@ -1336,4 +1336,4 @@ int fd_update_spll(fdelay_device_t *dev)
}
}
#endif
\ No newline at end of file
#endif
software/python/demo.py
View file @ c00e32c0
#!/usr/bin/python
#!/usr/bin/python2
import sys
import PyQt4
......@@ -70,9 +70,9 @@ def on_chk_wr():
if __name__ == "__main__":
app = QApplication(sys.argv)
if(sys.argv[1] == "1"):
location = "minibone/eth8/00:50:0c:de:bc:f8/0x100000"
location = "minibone/eth0/00:50:0c:de:bc:f8/0x100000"
else:
location = "minibone/eth8/00:50:e4:95:36:f8/0x100000"
location = "minibone/eth0/00:50:e4:95:36:f8/0x100000"
m = MainWindow()
m.show()
......
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