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FMC DEL 1ns 4cha
Commit a989eb86 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/top/svec: slot order according to the front panel. SDB addresses in… 

hdl/top/svec: slot order according to the front panel. SDB addresses in ascending order. Fixed wrong WR Core SDB bridge address.
parent 5a62a8fb
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hdl/syn/svec/wr/svec_fine_delay.xise
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......@@ -8,8 +9,9 @@
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......@@ -18,6 +20,7 @@
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......@@ -37,7 +40,7 @@
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......@@ -158,7 +161,6 @@
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......@@ -341,664 +347,736 @@
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<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wbp_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_gpio_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_tdp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_wb_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_wb_event.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_config.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_tlu/wb_cores_pkg_gsi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wr_tlu/wb_timestamp_latch.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
</file>
<file xil_pn:name="../../../top/svec/wr/svec_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/piso_flag.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/vhdl_2008_workaround_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="221"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="222"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/xetherbone_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="223"/>
</file>
<file xil_pn:name="../../../../../wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="224"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="225"/>
</file>
<file xil_pn:name="../../../../../wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="226"/>
</file>
<file xil_pn:name="../../../../../wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="227"/>
</file>
<file xil_pn:name="../../../../../wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
</file>
<file xil_pn:name="../../../../../wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="229"/>
</file>
<file xil_pn:name="../../../../../wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="230"/>
</file>
<file xil_pn:name="../../../../../wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
</file>
<file xil_pn:name="../../../../../wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="232"/>
</file>
<file xil_pn:name="../../../../../wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="233"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="234"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="235"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/eb_config.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="236"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="237"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="238"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="239"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="240"/>
</file>
<file xil_pn:name="../../../top/svec/wr/svec_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="241"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/piso_flag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="242"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/vhdl_2008_workaround_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="243"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/sipo_flag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="244"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="245"/>
</file>
<file xil_pn:name="../../../../../etherbone-core/hdl/eb_slave_core/xetherbone_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="246"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
</project>
hdl/top/svec/wr/svec_top.ucf
View file @ a989eb86
......@@ -321,13 +321,13 @@ NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
NET "tempid_dq_b" IOSTANDARD = "LVCMOS33";
NET "fmc1_prsntm2c_n_i" LOC = N30;
NET "fmc1_scl_b" LOC = P28;
NET "fmc1_sda_b" LOC = P30;
NET "fmc0_prsntm2c_n_i" LOC = N30;
NET "fmc0_scl_b" LOC = P28;
NET "fmc0_sda_b" LOC = P30;
NET "fmc0_prsntm2c_n_i" LOC = AE29;
NET "fmc0_scl_b" LOC = W29;
NET "fmc0_sda_b" LOC = V30;
NET "fmc1_prsntm2c_n_i" LOC = AE29;
NET "fmc1_scl_b" LOC = W29;
NET "fmc1_sda_b" LOC = V30;
......@@ -379,293 +379,294 @@ TIMESPEC TS_x6 = FROM "gen_with_phy_U_GTP_ch1_rx_divclk" TO "clk_125m_pllref_p_i
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 0
NET "fd1_clk_ref_p_i" LOC = "E16";
NET "fd1_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fd1_clk_ref_n_i" LOC = "D16";
NET "fd1_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fd1_tdc_start_p_i" LOC = "H15";
NET "fd1_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fd1_tdc_start_n_i" LOC = "G15";
NET "fd1_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fd1_delay_len_o[3]" LOC = "G10";
NET "fd1_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_len_o[2]" LOC = "F10";
NET "fd1_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_len_o[1]" LOC = "E9";
NET "fd1_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_len_o[0]" LOC = "F9";
NET "fd1_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_pulse_o[3]" LOC = "F12";
NET "fd1_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_pulse_o[1]" LOC = "E11";
NET "fd1_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_pulse_o[2]" LOC = "G12";
NET "fd1_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_pulse_o[0]" LOC = "F11";
NET "fd1_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[3]" LOC = "J12";
NET "fd1_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[1]" LOC = "H11";
NET "fd1_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[7]" LOC = "L11";
NET "fd1_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[5]" LOC = "J13";
NET "fd1_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[9]" LOC = "L12";
NET "fd1_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_mosi_o" LOC = "M13";
NET "fd1_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_sclk_o" LOC = "L14";
NET "fd1_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_oe_n_o" LOC = "M15";
NET "fd1_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_start_dis_o" LOC = "F13";
NET "fd1_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_cs_gpio_n_o" LOC = "F15";
NET "fd1_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_cal_pulse_o" LOC = "G14";
NET "fd1_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fd1_dmtd_clk_o" LOC = "J14";
NET "fd1_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_wr_n_o" LOC = "B15";
NET "fd1_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_alutrigger_o" LOC = "F19";
NET "fd1_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fd1_led_trig_o" LOC = "H16";
NET "fd1_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[26]" LOC = "F17";
NET "fd1_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[24]" LOC = "G18";
NET "fd1_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[20]" LOC = "F21";
NET "fd1_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[22]" LOC = "G20";
NET "fd1_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[18]" LOC = "L21";
NET "fd1_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[16]" LOC = "M20";
NET "fd1_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[10]" LOC = "F23";
NET "fd1_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[14]" LOC = "G22";
NET "fd1_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[8]" LOC = "B25";
NET "fd1_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[12]" LOC = "M19";
NET "fd1_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[3]" LOC = "D24";
NET "fd1_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[5]" LOC = "E25";
NET "fd1_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[7]" LOC = "J22";
NET "fd1_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[2]" LOC = "H21";
NET "fd1_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_trig_a_i" LOC = "C16";
NET "fd1_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[2]" LOC = "H12";
NET "fd1_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[0]" LOC = "G11";
NET "fd1_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[6]" LOC = "K11";
NET "fd1_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[4]" LOC = "H13";
NET "fd1_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[8]" LOC = "K12";
NET "fd1_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_miso_i" LOC = "L13";
NET "fd1_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_cs_pll_n_o" LOC = "K14";
NET "fd1_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_cs_dac_n_o" LOC = "K15";
NET "fd1_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_stop_dis_o" LOC = "E13";
NET "fd1_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fd1_ext_rst_n_o" LOC = "E15";
NET "fd1_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_pll_status_i" LOC = "F14";
NET "fd1_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fd1_dmtd_fb_out_i" LOC = "H14";
NET "fd1_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_rd_n_o" LOC = "A15";
NET "fd1_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_emptyf_i" LOC = "E19";
NET "fd1_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fd1_onewire_b" LOC = "G16";
NET "fd1_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[27]" LOC = "E17";
NET "fd1_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[25]" LOC = "F18";
NET "fd1_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[21]" LOC = "E21";
NET "fd1_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[23]" LOC = "F20";
NET "fd1_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[19]" LOC = "K21";
NET "fd1_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[17]" LOC = "L20";
NET "fd1_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[11]" LOC = "E23";
NET "fd1_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[15]" LOC = "F22";
NET "fd1_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[9]" LOC = "A25";
NET "fd1_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[13]" LOC = "L19";
NET "fd1_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[1]" LOC = "C24";
NET "fd1_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[4]" LOC = "D25";
NET "fd1_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[6]" LOC = "H22";
NET "fd1_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[0]" LOC = "G21";
NET "fd1_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_dmtd_fb_in_i" LOC = "A16";
NET "fd1_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
NET "fd0_clk_ref_p_i" LOC = "AH16";
NET "fd0_clk_ref_p_i" LOC = "E16";
NET "fd0_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fd0_clk_ref_n_i" LOC = "AK16";
NET "fd0_clk_ref_n_i" LOC = "D16";
NET "fd0_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fd0_tdc_start_p_i" LOC = "AF16";
NET "fd0_tdc_start_p_i" LOC = "H15";
NET "fd0_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fd0_tdc_start_n_i" LOC = "AG16";
NET "fd0_tdc_start_n_i" LOC = "G15";
NET "fd0_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fd0_delay_len_o[3]" LOC = "AB21";
NET "fd0_delay_len_o[3]" LOC = "G10";
NET "fd0_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_len_o[2]" LOC = "AC21";
NET "fd0_delay_len_o[2]" LOC = "F10";
NET "fd0_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_len_o[1]" LOC = "AD24";
NET "fd0_delay_len_o[1]" LOC = "E9";
NET "fd0_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_len_o[0]" LOC = "AC24";
NET "fd0_delay_len_o[0]" LOC = "F9";
NET "fd0_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_pulse_o[3]" LOC = "AE22";
NET "fd0_delay_pulse_o[3]" LOC = "F12";
NET "fd0_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_pulse_o[1]" LOC = "AD17";
NET "fd0_delay_pulse_o[1]" LOC = "E11";
NET "fd0_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_pulse_o[2]" LOC = "AD22";
NET "fd0_delay_pulse_o[2]" LOC = "G12";
NET "fd0_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_pulse_o[0]" LOC = "AB17";
NET "fd0_delay_pulse_o[0]" LOC = "F11";
NET "fd0_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[3]" LOC = "AA19";
NET "fd0_delay_val_o[3]" LOC = "J12";
NET "fd0_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[1]" LOC = "W19";
NET "fd0_delay_val_o[1]" LOC = "H11";
NET "fd0_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[7]" LOC = "Y21";
NET "fd0_delay_val_o[7]" LOC = "L11";
NET "fd0_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[5]" LOC = "W20";
NET "fd0_delay_val_o[5]" LOC = "J13";
NET "fd0_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[9]" LOC = "AA22";
NET "fd0_delay_val_o[9]" LOC = "L12";
NET "fd0_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fd0_spi_mosi_o" LOC = "AB20";
NET "fd0_spi_mosi_o" LOC = "M13";
NET "fd0_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fd0_spi_sclk_o" LOC = "AC19";
NET "fd0_spi_sclk_o" LOC = "L14";
NET "fd0_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_oe_n_o" LOC = "AF25";
NET "fd0_tdc_oe_n_o" LOC = "M15";
NET "fd0_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_start_dis_o" LOC = "AE24";
NET "fd0_tdc_start_dis_o" LOC = "F13";
NET "fd0_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fd0_spi_cs_gpio_n_o" LOC = "AE19";
NET "fd0_spi_cs_gpio_n_o" LOC = "F15";
NET "fd0_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_cal_pulse_o" LOC = "AE23";
NET "fd0_tdc_cal_pulse_o" LOC = "G14";
NET "fd0_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fd0_dmtd_clk_o" LOC = "AE21";
NET "fd0_dmtd_clk_o" LOC = "J14";
NET "fd0_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_wr_n_o" LOC = "AC16";
NET "fd0_tdc_wr_n_o" LOC = "B15";
NET "fd0_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_alutrigger_o" LOC = "AB14";
NET "fd0_tdc_alutrigger_o" LOC = "F19";
NET "fd0_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fd0_led_trig_o" LOC = "Y17";
NET "fd0_led_trig_o" LOC = "H16";
NET "fd0_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[26]" LOC = "Y15";
NET "fd0_tdc_d_b[26]" LOC = "F17";
NET "fd0_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[24]" LOC = "AC15";
NET "fd0_tdc_d_b[24]" LOC = "G18";
NET "fd0_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[20]" LOC = "AE15";
NET "fd0_tdc_d_b[20]" LOC = "F21";
NET "fd0_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[22]" LOC = "Y16";
NET "fd0_tdc_d_b[22]" LOC = "G20";
NET "fd0_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[18]" LOC = "Y14";
NET "fd0_tdc_d_b[18]" LOC = "L21";
NET "fd0_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[16]" LOC = "W14";
NET "fd0_tdc_d_b[16]" LOC = "M20";
NET "fd0_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[10]" LOC = "AB12";
NET "fd0_tdc_d_b[10]" LOC = "F23";
NET "fd0_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[14]" LOC = "AD12";
NET "fd0_tdc_d_b[14]" LOC = "G22";
NET "fd0_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[8]" LOC = "AD10";
NET "fd0_tdc_d_b[8]" LOC = "B25";
NET "fd0_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[12]" LOC = "AE11";
NET "fd0_tdc_d_b[12]" LOC = "M19";
NET "fd0_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[3]" LOC = "AJ15";
NET "fd0_tdc_d_b[3]" LOC = "D24";
NET "fd0_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[5]" LOC = "AE13";
NET "fd0_tdc_d_b[5]" LOC = "E25";
NET "fd0_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[7]" LOC = "AC11";
NET "fd0_tdc_d_b[7]" LOC = "J22";
NET "fd0_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[2]" LOC = "AG8";
NET "fd0_tdc_d_b[2]" LOC = "H21";
NET "fd0_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fd0_trig_a_i" LOC = "AJ17";
NET "fd0_trig_a_i" LOC = "C16";
NET "fd0_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[2]" LOC = "AB19";
NET "fd0_delay_val_o[2]" LOC = "H12";
NET "fd0_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[0]" LOC = "Y19";
NET "fd0_delay_val_o[0]" LOC = "G11";
NET "fd0_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[6]" LOC = "AA21";
NET "fd0_delay_val_o[6]" LOC = "K11";
NET "fd0_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[4]" LOC = "Y20";
NET "fd0_delay_val_o[4]" LOC = "H13";
NET "fd0_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[8]" LOC = "AC22";
NET "fd0_delay_val_o[8]" LOC = "K12";
NET "fd0_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fd0_spi_miso_i" LOC = "AC20";
NET "fd0_spi_miso_i" LOC = "L13";
NET "fd0_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fd0_spi_cs_pll_n_o" LOC = "AD19";
NET "fd0_spi_cs_pll_n_o" LOC = "K14";
NET "fd0_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_spi_cs_dac_n_o" LOC = "AG25";
NET "fd0_spi_cs_dac_n_o" LOC = "K15";
NET "fd0_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_stop_dis_o" LOC = "AF24";
NET "fd0_tdc_stop_dis_o" LOC = "E13";
NET "fd0_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fd0_ext_rst_n_o" LOC = "AF19";
NET "fd0_ext_rst_n_o" LOC = "E15";
NET "fd0_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_pll_status_i" LOC = "AF23";
NET "fd0_pll_status_i" LOC = "F14";
NET "fd0_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fd0_dmtd_fb_out_i" LOC = "AF21";
NET "fd0_dmtd_fb_out_i" LOC = "H14";
NET "fd0_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_rd_n_o" LOC = "AD16";
NET "fd0_tdc_rd_n_o" LOC = "A15";
NET "fd0_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_emptyf_i" LOC = "AC14";
NET "fd0_tdc_emptyf_i" LOC = "E19";
NET "fd0_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fd0_onewire_b" LOC = "AA17";
NET "fd0_onewire_b" LOC = "G16";
NET "fd0_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[27]" LOC = "AA15";
NET "fd0_tdc_d_b[27]" LOC = "E17";
NET "fd0_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[25]" LOC = "AD15";
NET "fd0_tdc_d_b[25]" LOC = "F18";
NET "fd0_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[21]" LOC = "AF15";
NET "fd0_tdc_d_b[21]" LOC = "E21";
NET "fd0_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[23]" LOC = "AB16";
NET "fd0_tdc_d_b[23]" LOC = "F20";
NET "fd0_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[19]" LOC = "AA14";
NET "fd0_tdc_d_b[19]" LOC = "K21";
NET "fd0_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[17]" LOC = "Y13";
NET "fd0_tdc_d_b[17]" LOC = "L20";
NET "fd0_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[11]" LOC = "AC12";
NET "fd0_tdc_d_b[11]" LOC = "E23";
NET "fd0_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[15]" LOC = "AE12";
NET "fd0_tdc_d_b[15]" LOC = "F22";
NET "fd0_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[9]" LOC = "AE10";
NET "fd0_tdc_d_b[9]" LOC = "A25";
NET "fd0_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[13]" LOC = "AF11";
NET "fd0_tdc_d_b[13]" LOC = "L19";
NET "fd0_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[1]" LOC = "AK15";
NET "fd0_tdc_d_b[1]" LOC = "C24";
NET "fd0_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[4]" LOC = "AF13";
NET "fd0_tdc_d_b[4]" LOC = "D25";
NET "fd0_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[6]" LOC = "AD11";
NET "fd0_tdc_d_b[6]" LOC = "H22";
NET "fd0_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[0]" LOC = "AH8";
NET "fd0_tdc_d_b[0]" LOC = "G21";
NET "fd0_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fd0_dmtd_fb_in_i" LOC = "AK17";
NET "fd0_dmtd_fb_in_i" LOC = "A16";
NET "fd0_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
NET "fd1_clk_ref_p_i" LOC = "AH16";
NET "fd1_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fd1_clk_ref_n_i" LOC = "AK16";
NET "fd1_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fd1_tdc_start_p_i" LOC = "AF16";
NET "fd1_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fd1_tdc_start_n_i" LOC = "AG16";
NET "fd1_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fd1_delay_len_o[3]" LOC = "AB21";
NET "fd1_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_len_o[2]" LOC = "AC21";
NET "fd1_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_len_o[1]" LOC = "AD24";
NET "fd1_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_len_o[0]" LOC = "AC24";
NET "fd1_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_pulse_o[3]" LOC = "AE22";
NET "fd1_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_pulse_o[1]" LOC = "AD17";
NET "fd1_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_pulse_o[2]" LOC = "AD22";
NET "fd1_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_pulse_o[0]" LOC = "AB17";
NET "fd1_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[3]" LOC = "AA19";
NET "fd1_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[1]" LOC = "W19";
NET "fd1_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[7]" LOC = "Y21";
NET "fd1_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[5]" LOC = "W20";
NET "fd1_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[9]" LOC = "AA22";
NET "fd1_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_mosi_o" LOC = "AB20";
NET "fd1_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_sclk_o" LOC = "AC19";
NET "fd1_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_oe_n_o" LOC = "AF25";
NET "fd1_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_start_dis_o" LOC = "AE24";
NET "fd1_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_cs_gpio_n_o" LOC = "AE19";
NET "fd1_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_cal_pulse_o" LOC = "AE23";
NET "fd1_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fd1_dmtd_clk_o" LOC = "AE21";
NET "fd1_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_wr_n_o" LOC = "AC16";
NET "fd1_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_alutrigger_o" LOC = "AB14";
NET "fd1_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fd1_led_trig_o" LOC = "Y17";
NET "fd1_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[26]" LOC = "Y15";
NET "fd1_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[24]" LOC = "AC15";
NET "fd1_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[20]" LOC = "AE15";
NET "fd1_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[22]" LOC = "Y16";
NET "fd1_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[18]" LOC = "Y14";
NET "fd1_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[16]" LOC = "W14";
NET "fd1_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[10]" LOC = "AB12";
NET "fd1_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[14]" LOC = "AD12";
NET "fd1_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[8]" LOC = "AD10";
NET "fd1_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[12]" LOC = "AE11";
NET "fd1_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[3]" LOC = "AJ15";
NET "fd1_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[5]" LOC = "AE13";
NET "fd1_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[7]" LOC = "AC11";
NET "fd1_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[2]" LOC = "AG8";
NET "fd1_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_trig_a_i" LOC = "AJ17";
NET "fd1_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[2]" LOC = "AB19";
NET "fd1_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[0]" LOC = "Y19";
NET "fd1_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[6]" LOC = "AA21";
NET "fd1_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[4]" LOC = "Y20";
NET "fd1_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[8]" LOC = "AC22";
NET "fd1_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_miso_i" LOC = "AC20";
NET "fd1_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_cs_pll_n_o" LOC = "AD19";
NET "fd1_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_cs_dac_n_o" LOC = "AG25";
NET "fd1_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_stop_dis_o" LOC = "AF24";
NET "fd1_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fd1_ext_rst_n_o" LOC = "AF19";
NET "fd1_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_pll_status_i" LOC = "AF23";
NET "fd1_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fd1_dmtd_fb_out_i" LOC = "AF21";
NET "fd1_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_rd_n_o" LOC = "AD16";
NET "fd1_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_emptyf_i" LOC = "AC14";
NET "fd1_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fd1_onewire_b" LOC = "AA17";
NET "fd1_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[27]" LOC = "AA15";
NET "fd1_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[25]" LOC = "AD15";
NET "fd1_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[21]" LOC = "AF15";
NET "fd1_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[23]" LOC = "AB16";
NET "fd1_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[19]" LOC = "AA14";
NET "fd1_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[17]" LOC = "Y13";
NET "fd1_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[11]" LOC = "AC12";
NET "fd1_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[15]" LOC = "AE12";
NET "fd1_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[9]" LOC = "AE10";
NET "fd1_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[13]" LOC = "AF11";
NET "fd1_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[1]" LOC = "AK15";
NET "fd1_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[4]" LOC = "AF13";
NET "fd1_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[6]" LOC = "AD11";
NET "fd1_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[0]" LOC = "AH8";
NET "fd1_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_dmtd_fb_in_i" LOC = "AK17";
NET "fd1_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
hdl/top/svec/wr/svec_top.vhd
View file @ a989eb86
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-04-16
-- Last update: 2013-05-17
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -325,20 +325,21 @@ architecture rtl of svec_top is
constant c_MASTER_VME : integer := 0;
constant c_MASTER_ETHERBONE : integer := 1;
constant c_SLAVE_FD1 : integer := 0;
constant c_SLAVE_FD0 : integer := 1;
constant c_SLAVE_WRCORE : integer := 2;
constant c_SLAVE_VIC : integer := 3;
constant c_SLAVE_FD1 : integer := 1;
constant c_SLAVE_FD0 : integer := 0;
constant c_SLAVE_WRCORE : integer := 3;
constant c_SLAVE_VIC : integer := 2;
constant c_DESC_SYNTHESIS : integer := 4;
constant c_DESC_REPO_URL : integer := 5;
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00040000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00070000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 1 downto 0) :=
(c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"00040000"),
(
c_SLAVE_FD0 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00010000"),
c_SLAVE_FD1 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00020000"),
c_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00030000"),
c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"00040000"),
c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
c_DESC_REPO_URL => f_sdb_embed_repo_url(c_sdb_repo_url)
);
......@@ -660,7 +661,7 @@ begin
g_aux_clks => 2,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_softpll_enable_debugger => true,
-- g_softpll_enable_debugger => true,
g_dpram_initf => "none")
port map (
clk_sys_i => clk_sys,
......@@ -723,9 +724,9 @@ begin
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked,
tm_dac_wr_o => tm_dac_wr(0),
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en(0),
tm_clk_aux_locked_o => tm_clk_aux_locked(0),
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_utc,
tm_cycles_o => tm_cycles,
......@@ -1053,7 +1054,7 @@ begin
tm_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the
-- -- WRCore
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr(1),
tm_dac_wr_i => '0',
owr_en_o => fd1_owr_en,
owr_i => fd1_owr_in,
......
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