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FMC DEL 1ns 4cha
Commit 9b7a0f77 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge remote-tracking branch 'origin/tom-spec-convention' into dlamprid-wrtd-dev

parents eca0894f 018715ac
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.gitmodules
View file @ 9b7a0f77
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
doc/design-notes/fd_main_regs.in
View file @ 9b7a0f77
......@@ -354,6 +354,26 @@ Stop disable
@code{ALUTRIG}
@tab @code{0} @tab
Pulse <code>Alutrigger</code> line
@item @code{8}
@tab W/O @tab
@code{IDELAY_CE}
@tab @code{0} @tab
IDELAY CE (pulse)
@item @code{9}
@tab R/W @tab
@code{IDELAY_RST}
@tab @code{0} @tab
IDELAY RST (GPIO)
@item @code{10}
@tab R/W @tab
@code{IDELAY_CAL}
@tab @code{0} @tab
IDELAY CAL (GPIO)
@item @code{11}
@tab R/W @tab
@code{IDELAY_INC}
@tab @code{0} @tab
IDELAY CAL (GPIO)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -365,6 +385,10 @@ Pulse <code>Alutrigger</code> line
@item @code{START_EN} @tab Controls the @code{StartDis} input of the TDC.@* write 1: enables the TDC start input.@* write 0: no effect.
@item @code{STOP_DIS} @tab Controls the @code{StopDis} input of the TDC.@* write 1: disables the TDC stop input.@* write 0: no effect.
@item @code{ALUTRIG} @tab Controls the TDC's @code{Alutrigger} line. Depending on the TDC's configuration, it can be used as a reset/FIFO clear/trigger signal.@* write 1: generates a pulse ACAM's @code{Alutrigger} line@* write 0: no effect.
@item @code{IDELAY_CE} @tab Write 1 to pulse the IDELAY CE line for 1 clock tick.
@item @code{IDELAY_RST} @tab State of IDELAY RST line
@item @code{IDELAY_CAL} @tab State of IDELAY CAL line
@item @code{IDELAY_INC} @tab State of IDELAY INC line
@end multitable
@regsection @code{CALR} - Calibration register
Controls calibration logic.
......
hdl/include/jittery_delay.svh
View file @ 9b7a0f77
`timescale 10fs/10fs
module jittery_delay
(
......
hdl/include/regs/fd_main_regs.vh
View file @ 9b7a0f77
......@@ -12,7 +12,7 @@
`define FD_GCR_INPUT_EN_OFFSET 1
`define FD_GCR_INPUT_EN 32'h00000002
`define FD_GCR_DDR_LOCKED_OFFSET 2
`define FD_GCR_DDR_LOCKED 32'h00000004
`define FD_GCR_DDR_LOCKED 32'h0000CAL0004
`define FD_GCR_FMC_PRESENT_OFFSET 3
`define FD_GCR_FMC_PRESENT 32'h00000008
`define ADDR_FD_TCR 8'hc
......@@ -53,6 +53,14 @@
`define FD_TDCSR_STOP_DIS 32'h00000040
`define FD_TDCSR_ALUTRIG_OFFSET 7
`define FD_TDCSR_ALUTRIG 32'h00000080
`define FD_TDCSR_IDELAY_CE_OFFSET 8
`define FD_TDCSR_IDELAY_CE 32'h00000100
`define FD_TDCSR_IDELAY_RST_OFFSET 9
`define FD_TDCSR_IDELAY_RST 32'h00000200
`define FD_TDCSR_IDELAY_CAL_OFFSET 10
`define FD_TDCSR_IDELAY_CAL 32'h00000400
`define FD_TDCSR_IDELAY_INC_OFFSET 11
`define FD_TDCSR_IDELAY_INC 32'h00000800
`define ADDR_FD_CALR 8'h24
`define FD_CALR_CAL_PULSE_OFFSET 0
`define FD_CALR_CAL_PULSE 32'h00000001
......
hdl/include/tunable_clock_gen.svh
View file @ 9b7a0f77
......@@ -10,8 +10,8 @@ module tunable_clock_gen
parameter g_tunable = 0;
parameter g_tuning_range = 20e-6; // 20 ppm
parameter g_tuning_voltage = 1.0;
parameter real g_period = 8ns;
parameter real g_jitter = 10ps;
parameter time g_period = 8ns;
parameter time g_jitter = 10ps;
reg clk = 1'b1;
......
ddr3-sp6-core @ 1a129390
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
spec @ 13afc710
Subproject commit 13afc71072f38174e9f738c081cdb4fdc82a07dc
hdl/rtl/fd_acam_timestamper.vhd
View file @ 9b7a0f77
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-07-02
-- Last update: 2019-03-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -423,21 +423,10 @@ begin -- behave
-- Input: tdc_start_i
-- Output: tdc_start_d
--
-- A synchronizer chain for detecting the relation between clk_tdc_i
-- and clk_ref_i. Since both clocks are almost in phase, the first stage
-- reacts to the falling edge of the reference clock to satisfy setup/hold
-- requirements.
--
p_sync_tdclk_fedge : process(clk_ref_i)
begin
if falling_edge(clk_ref_i) then
tdc_start_d(0) <= tdc_start_i;
end if;
end process;
p_sync_tdclk_redge : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
tdc_start_d(0) <= tdc_start_i;
tdc_start_d(1) <= tdc_start_d(0);
tdc_start_d(2) <= tdc_start_d(1);
end if;
......
hdl/rtl/fd_channel_wbgen2_pkg.vhd
View file @ 9b7a0f77
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:17 2013
-- Created : Wed Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -78,37 +78,63 @@ package fd_channel_wbgen2_pkg is
rcr_rep_cnt_o => (others => '0'),
rcr_cont_o => '0'
);
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component fd_channel_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
end component;
end package;
package body fd_channel_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers is
variable tmp: t_fd_channel_in_registers;
variable tmp: t_fd_channel_in_registers;
begin
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
end function;
end package body;
hdl/rtl/fd_channel_wishbone_slave.vhd
View file @ 9b7a0f77
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:17 2013
-- Created : Wed Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -18,7 +18,7 @@ use work.fd_channel_wbgen2_pkg.all;
entity fd_channel_wb_slave is
port (
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
......@@ -29,11 +29,13 @@ entity fd_channel_wb_slave is
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
);
end fd_channel_wb_slave;
architecture syn of fd_channel_wb_slave is
......@@ -94,17 +96,12 @@ signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
......@@ -490,15 +487,15 @@ begin
end if;
end if;
end if;
end process;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
wb_dat_o <= rddata_reg;
-- Enable channel
-- synchronizer chain for field : Enable channel (type RW/RO, clk_sys_i <-> clk_ref_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_enable_o <= '0';
fd_channel_dcr_enable_sync0 <= '0';
......@@ -508,14 +505,14 @@ begin
fd_channel_dcr_enable_sync1 <= fd_channel_dcr_enable_sync0;
regs_o.dcr_enable_o <= fd_channel_dcr_enable_sync1;
end if;
end process;
end process;
-- Delay mode select
regs_o.dcr_mode_o <= fd_channel_dcr_mode_int;
regs_o.dcr_mode_o <= fd_channel_dcr_mode_int;
-- Pulse generator arm
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_pg_arm_o <= '0';
fd_channel_dcr_pg_arm_sync0 <= '0';
......@@ -527,13 +524,13 @@ begin
fd_channel_dcr_pg_arm_sync2 <= fd_channel_dcr_pg_arm_sync1;
regs_o.dcr_pg_arm_o <= fd_channel_dcr_pg_arm_sync2 and (not fd_channel_dcr_pg_arm_sync1);
end if;
end process;
end process;
-- Pulse generator triggered
-- synchronizer chain for field : Pulse generator triggered (type RO/WO, clk_ref_i -> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_dcr_pg_trig_sync0 <= '0';
fd_channel_dcr_pg_trig_sync1 <= '0';
......@@ -541,12 +538,12 @@ begin
fd_channel_dcr_pg_trig_sync0 <= regs_i.dcr_pg_trig_i;
fd_channel_dcr_pg_trig_sync1 <= fd_channel_dcr_pg_trig_sync0;
end if;
end process;
end process;
-- Update delay/absolute trigger time
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_update_o <= '0';
fd_channel_dcr_update_sync0 <= '0';
......@@ -558,13 +555,13 @@ begin
fd_channel_dcr_update_sync2 <= fd_channel_dcr_update_sync1;
regs_o.dcr_update_o <= fd_channel_dcr_update_sync2 and (not fd_channel_dcr_update_sync1);
end if;
end process;
end process;
-- Delay update done flag
-- synchronizer chain for field : Delay update done flag (type RO/WO, clk_ref_i -> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_dcr_upd_done_sync0 <= '0';
fd_channel_dcr_upd_done_sync1 <= '0';
......@@ -572,12 +569,12 @@ begin
fd_channel_dcr_upd_done_sync0 <= regs_i.dcr_upd_done_i;
fd_channel_dcr_upd_done_sync1 <= fd_channel_dcr_upd_done_sync0;
end if;
end process;
end process;
-- Force calibration delay
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_force_dly_o <= '0';
fd_channel_dcr_force_dly_sync0 <= '0';
......@@ -589,17 +586,17 @@ begin
fd_channel_dcr_force_dly_sync2 <= fd_channel_dcr_force_dly_sync1;
regs_o.dcr_force_dly_o <= fd_channel_dcr_force_dly_sync2 and (not fd_channel_dcr_force_dly_sync1);
end if;
end process;
end process;
-- Disable fine part update
regs_o.dcr_no_fine_o <= fd_channel_dcr_no_fine_int;
regs_o.dcr_no_fine_o <= fd_channel_dcr_no_fine_int;
-- Force output high
regs_o.dcr_force_hi_o <= fd_channel_dcr_force_hi_int;
regs_o.dcr_force_hi_o <= fd_channel_dcr_force_hi_int;
-- Fine range in SY89825 taps.
-- asynchronous std_logic_vector register : Fine range in SY89825 taps. (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_frr_swb_s0 <= '0';
fd_channel_frr_swb_s1 <= '0';
......@@ -613,37 +610,39 @@ begin
regs_o.frr_o <= fd_channel_frr_int;
end if;
end if;
end process;
end process;
-- TAI seconds (MSB)
regs_o.u_starth_o <= fd_channel_u_starth_int;
regs_o.u_starth_o <= fd_channel_u_starth_int;
-- TAI seconds (LSB)
regs_o.u_startl_o <= fd_channel_u_startl_int;
regs_o.u_startl_o <= fd_channel_u_startl_int;
-- Reference clock cycles
regs_o.c_start_o <= fd_channel_c_start_int;
regs_o.c_start_o <= fd_channel_c_start_int;
-- Fractional part
regs_o.f_start_o <= fd_channel_f_start_int;
regs_o.f_start_o <= fd_channel_f_start_int;
-- TAI seconds (MSB)
regs_o.u_endh_o <= fd_channel_u_endh_int;
regs_o.u_endh_o <= fd_channel_u_endh_int;
-- TAI seconds (LSB)
regs_o.u_endl_o <= fd_channel_u_endl_int;
regs_o.u_endl_o <= fd_channel_u_endl_int;
-- Reference clock cycles
regs_o.c_end_o <= fd_channel_c_end_int;
regs_o.c_end_o <= fd_channel_c_end_int;
-- Fractional part
regs_o.f_end_o <= fd_channel_f_end_int;
regs_o.f_end_o <= fd_channel_f_end_int;
-- TAI seconds
regs_o.u_delta_o <= fd_channel_u_delta_int;
regs_o.u_delta_o <= fd_channel_u_delta_int;
-- Reference clock cycles
regs_o.c_delta_o <= fd_channel_c_delta_int;
regs_o.c_delta_o <= fd_channel_c_delta_int;
-- Fractional part
regs_o.f_delta_o <= fd_channel_f_delta_int;
regs_o.f_delta_o <= fd_channel_f_delta_int;
-- Repeat Count
regs_o.rcr_rep_cnt_o <= fd_channel_rcr_rep_cnt_int;
regs_o.rcr_rep_cnt_o <= fd_channel_rcr_rep_cnt_int;
-- Continuous Waveform Mode
regs_o.rcr_cont_o <= fd_channel_rcr_cont_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
regs_o.rcr_cont_o <= fd_channel_rcr_cont_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
wb_ack_o <= ack_sreg(0);
end syn;
hdl/rtl/fd_delay_channel_driver.vhd
View file @ 9b7a0f77
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2018-07-18
-- Last update: 2019-09-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ 9b7a0f77
This diff is collapsed.
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ 9b7a0f77
This diff is collapsed.
hdl/rtl/fd_main_wishbone_slave.wb
View file @ 9b7a0f77
......@@ -404,6 +404,47 @@ peripheral {
prefix = "ALUTRIG";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "IDELAY CE (pulse)";
description = "Write 1 to pulse the IDELAY CE line for 1 clock tick.";
prefix = "IDELAY_CE";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "IDELAY RST (GPIO)";
description = "State of IDELAY RST line";
prefix = "IDELAY_RST";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
clock = "clk_ref_i";
name = "IDELAY CAL (GPIO)";
description = "State of IDELAY CAL line";
prefix = "IDELAY_CAL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
clock = "clk_ref_i";
name = "IDELAY CAL (GPIO)";
description = "State of IDELAY INC line";
prefix = "IDELAY_INC";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......@@ -1031,6 +1072,20 @@ peripheral {
};
};
reg {
name = "FMC Slot ID Register";
description = "Index of the hardware FMC slot the card is in.";
prefix = "FMC_SLOT_ID";
field {
name = "Slot ID";
prefix = "SLOT_ID";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
irq {
name = "Timestamp Buffer interrupt.";
......
hdl/rtl/fine_delay_core.vhd
View file @ 9b7a0f77
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2018-08-03
-- Last update: 2019-09-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -65,7 +65,11 @@ entity fine_delay_core is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_debug_output : boolean := false
g_with_debug_output : boolean := false;
-- index of the slot the core is assigned to, written to
-- FMC_SLOT_ID register
g_fmc_slot_id : integer := 0
);
port (
......@@ -195,7 +199,7 @@ entity fine_delay_core is
owr_i : in std_logic;
---------------------------------------------------------------------------
-- Misc signals: I2C EEPROM, FMC presence
-- Misc signals: I2C EEPROM, FMC presence, I/O calibration
---------------------------------------------------------------------------
i2c_scl_o : out std_logic;
......@@ -207,6 +211,11 @@ entity fine_delay_core is
fmc_present_n_i : in std_logic;
idelay_inc_o : out std_logic;
idelay_cal_o : out std_logic;
idelay_ce_o : out std_logic;
idelay_rst_o : out std_logic;
---------------------------------------------------------------------------
-- Wishbone slave (classic/pipelined)
......@@ -504,6 +513,12 @@ begin -- rtl
);
idelay_rst_o <= regs_fromwb.tdcsr_idelay_rst_o;
idelay_ce_o <= regs_fromwb.tdcsr_idelay_ce_o;
idelay_inc_o <= regs_fromwb.tdcsr_idelay_inc_o and regs_fromwb.tdcsr_idelay_ce_o;
idelay_cal_o <= regs_fromwb.tdcsr_idelay_cal_o;
U_Acam_TSU : fd_acam_timestamper
generic map (
g_min_pulse_width => 3,
......@@ -780,6 +795,7 @@ begin -- rtl
regs_towb_local.gcr_ddr_locked_i <= pll_status_i;
regs_towb_local.gcr_fmc_present_i <= not fmc_present_n_i;
regs_towb_local.fmc_slot_id_slot_id_i <= std_logic_vector(to_unsigned(g_fmc_slot_id, 4 ));
-- Debug PWM driver for adjusting Peltier temperature. Drivers SPI MOSI line
-- with PWM waveform when none of the SPI peripherals is in use (we have no
......
hdl/rtl/fine_delay_pkg.vhd
View file @ 9b7a0f77
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2014-03-24
-- Last update: 2019-03-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -237,32 +237,6 @@ package fine_delay_pkg is
regs_o : out t_fd_channel_out_registers);
end component;
component fd_main_wb_slave
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_ref_i : in std_logic;
tcr_rd_ack_o : out std_logic;
dmtr_in_rd_ack_o : out std_logic;
dmtr_out_rd_ack_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
irq_dmtd_spll_i : in std_logic;
irq_sync_status_i : in std_logic;
regs_i : in t_fd_main_in_registers;
regs_o : out t_fd_main_out_registers);
end component;
component fd_delay_line_arbiter
port (
......@@ -436,6 +410,10 @@ package fine_delay_pkg is
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
fmc_present_n_i : in std_logic;
idelay_inc_o : out std_logic;
idelay_cal_o : out std_logic;
idelay_ce_o : out std_logic;
idelay_rst_o : out std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
......
hdl/syn/spec/Manifest.py
View file @ 9b7a0f77
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_fine_delay.xise"
syn_tool = "ise"
syn_top = "spec_top"
spec_template_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../top/spec" ]
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
modules = { "local" : [ "../../top/spec", "../../platform" ] }
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/spec/spec_fine_delay.xise
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hdl/syn/svec/Manifest.py
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......@@ -8,8 +8,7 @@ syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top"
syn_project = "svec_fine_delay.xise"
syn_tool="ise"
syn_tool = "ise"
files = [ "wrc-release.ram" ]
#files = [ "wrc-release.ram" ]
modules = { "local" : [ "../../top/svec", "../../platform" ] }
hdl/syn/svec/svec_fine_delay.xise
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This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/svec/wrc-release.ram deleted 100644 → 0
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hdl/testbench/svec_wr_top/Manifest.py
View file @ 9b7a0f77
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include"
sim_tool="modelsim"
sim_top="main"
include_dirs = ["../../include/wb", "../../include/vme64x_bfm", "../../include" ];
syn_device="xc6slx150t"
files = [ "main.sv" ]
......
hdl/testbench/svec_wr_top/main.sv
View file @ 9b7a0f77
......@@ -182,6 +182,8 @@ module main;
drv0 = new(acc, 'h80010000);
drv0.init();
drv0.set_idelay_taps(30);
t_start=new;
drv0.get_time(t_start);
t_start.coarse += 20000;
......
hdl/testbench/svec_wr_top/run.do
View file @ 9b7a0f77
vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include
vsim work.main -voptargs=+acc
vsim -t 1ps work.main -novopt -L unisim
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
......
hdl/testbench/svec_wr_top/simdrv_fine_delay.svh
View file @ 9b7a0f77
......@@ -40,6 +40,33 @@ class CSimDrv_FineDelay;
endfunction // new
task set_idelay_taps( int taps );
uint64_t tdcsr;
readl(`ADDR_FD_TDCSR, tdcsr);
// calibrate the iodelay
writel( `ADDR_FD_TDCSR , tdcsr | `FD_TDCSR_IDELAY_CAL );
#3us;
writel( `ADDR_FD_TDCSR , tdcsr );
$display("Set IDELAY tap count = %d", taps);
writel( `ADDR_FD_TDCSR, tdcsr | `FD_TDCSR_IDELAY_RST );
writel( `ADDR_FD_TDCSR, tdcsr | `FD_TDCSR_IDELAY_INC );
for(int i = 0; i<taps;i++)
begin
writel(`ADDR_FD_TDCSR , tdcsr | `FD_TDCSR_IDELAY_CE | `FD_TDCSR_IDELAY_INC );
#1us;
end
endtask // set_idelay_taps
/* fixme - maybe use real mcp23s17 model instead of this stub? */
task sgpio_write(int value);
uint64_t scr;
......
hdl/testbench/svec_wr_top/wave.do
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This diff is collapsed.
hdl/top/spec/Manifest.py
View file @ 9b7a0f77
files = ["synthesis_descriptor.vhd", "spec_top.vhd", "spec_top.ucf", "spec_reset_gen.vhd"]
files = ["spec_top.vhd", "spec_top.ucf"]
fetchto = "../../ip_cores"
......@@ -6,10 +6,11 @@ modules = {
"local" : [
"../../rtl",
"../../platform",
],
"git" : [
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"git://ohwr.org/hdl-core-lib/general-cores.git",
],
}
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/spec",
"../../ip_cores/gn4124-core",
"../../ip_cores/spec",
"../../ip_cores/ddr3-sp6-core"
]
}
hdl/top/spec/spec_reset_gen.vhd deleted 100644 → 0
View file @ eca0894f
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
hdl/top/spec/spec_top.ucf
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hdl/top/spec/spec_top.vhd
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hdl/top/spec/synthesis_descriptor.vhd deleted 100644 → 0
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-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCIe FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec-fine-delay ",
syn_commit_id => "7dd0a8c348dee0a3a660143c80487a8a",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20141209",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git "
);
end package synthesis_descriptor;
hdl/top/svec/svec_top.vhd
View file @ 9b7a0f77
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2018-07-19
-- Last update: 2019-09-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -51,6 +51,7 @@ use work.vme64x_pkg.all;
use work.fine_delay_pkg.all;
--use work.etherbone_pkg.all;
use work.wr_xilinx_pkg.all;
use work.vme64x_pkg.all;
use work.synthesis_descriptor.all;
......@@ -61,7 +62,8 @@ entity svec_top is
generic
(
g_with_wr_phy : integer := 1;
g_simulation : integer := 0
g_simulation : integer := 0;
g_SIM_BYPASS_VME : integer := 0
);
port
(
......@@ -243,6 +245,12 @@ entity svec_top is
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic
-- Bypass VME core, useful only in simulation
-- synthesis translate_off
;
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out
-- synthesis translate_on
);
end svec_top;
......@@ -306,12 +314,12 @@ architecture rtl of svec_top is
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
signal phy_tx_k : std_logic_vector(0 downto 0);
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic;
signal phy_rx_k : std_logic_vector(0 downto 0);
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
......@@ -357,11 +365,23 @@ architecture rtl of svec_top is
signal dcm0_clk_ref_0, dcm0_clk_ref_180 : std_logic;
signal fd0_tdc_start : std_logic;
signal fd0_tdc_start_predelay : std_logic;
signal fd0_tdc_start_iodelay_inc : std_logic;
signal fd0_tdc_start_iodelay_rst : std_logic;
signal fd0_tdc_start_iodelay_cal : std_logic;
signal fd0_tdc_start_iodelay_ce : std_logic;
signal tdc0_data_out, tdc0_data_in : std_logic_vector(27 downto 0);
signal tdc0_data_oe : std_logic;
signal dcm1_clk_ref_0, dcm1_clk_ref_180 : std_logic;
signal fd1_tdc_start : std_logic;
signal fd1_tdc_start_predelay : std_logic;
signal fd1_tdc_start_iodelay_inc : std_logic;
signal fd1_tdc_start_iodelay_rst : std_logic;
signal fd1_tdc_start_iodelay_cal : std_logic;
signal fd1_tdc_start_iodelay_ce : std_logic;
signal tdc1_data_out, tdc1_data_in : std_logic_vector(27 downto 0);
signal tdc1_data_oe : std_logic;
......@@ -590,6 +610,7 @@ begin
I => clk_20m_vcxo_i);
gen_with_vme64_core : if g_SIM_BYPASS_VME = 0 generate
U_VME_Core : xvme64x_core
generic map (
g_CLOCK_PERIOD => 16,
......@@ -602,9 +623,9 @@ begin
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map (
clk_i => clk_sys,
rst_n_i => powerup_rst_n,
rst_n_i => local_reset_n,
vme_i.as_n => VME_AS_n_i,
vme_i.rst_n => powerup_rst_n,
vme_i.rst_n => VME_RST_n_i,
vme_i.write_n => VME_WRITE_n_i,
vme_i.am => VME_AM_i,
vme_i.ds_n => VME_DS_n_i,
......@@ -628,8 +649,8 @@ begin
vme_o.data_oe_n => VME_DATA_OE_N_o,
vme_o.addr_dir => VME_ADDR_DIR_int,
vme_o.addr_oe_n => VME_ADDR_OE_N_o,
wb_o => vme_master_out,
wb_i => vme_master_in,
wb_o => cnx_slave_in(c_MASTER_VME),
wb_i => cnx_slave_out(c_MASTER_VME),
int_i => vic_master_irq);
VME_DATA_b <= VME_DATA_b_out when VME_DATA_DIR_int = '1' else (others => 'Z');
......@@ -642,9 +663,14 @@ begin
-- BERR and IRQ vme signals are inverted by the drivers. See SVEC schematics.
VME_BERR_o <= not VME_BERR_n;
VME_IRQ_n_o <= not VME_IRQ_n;
end generate gen_with_vme64_core;
cnx_slave_in(c_MASTER_VME) <= vme_master_out;
vme_master_in <= cnx_slave_out(c_MASTER_VME);
gen_without_vme64_core : if g_SIM_BYPASS_VME /= 0 generate
-- synthesis translate_off
cnx_slave_in(c_MASTER_VME) <= sim_wb_i;
sim_wb_o <= cnx_slave_out(c_MASTER_VME);
-- synthesis translate_on
end generate gen_without_vme64_core;
-- Tristates for FMC0 EEPROM: fixme: wire to WRCore
fmc0_scl_b <= '0' when (fd0_scl_out = '0') else 'Z';
......@@ -861,12 +887,12 @@ begin
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k,
ch1_tx_k_i => phy_tx_k(0),
ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k,
ch1_rx_k_o => phy_rx_k(0),
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
......@@ -892,11 +918,32 @@ begin
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => fd0_tdc_start, -- Buffer output
O => fd0_tdc_start_predelay, -- Buffer output
I => fd0_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fd0_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
);
cmp_fd_tdc_start_delay0 : IODELAY2
generic map (
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
DATA_RATE => "SDR"
)
port map (
IDATAIN => fd0_tdc_start_predelay,
DATAOUT2 => fd0_tdc_start,
INC => fd0_tdc_start_iodelay_inc,
CE => fd0_tdc_start_iodelay_ce,
RST => fd0_tdc_start_iodelay_rst,
CLK => dcm0_clk_ref_0,
ODATAIN => '0',
CAL => fd0_tdc_start_iodelay_cal,
T => '1',
IOCLK0 => dcm0_clk_ref_0,
IOCLK1 => '0'
);
U_DDR_PLL0 : fd_ddr_pll
port map (
RST => ddr0_pll_reset,
......@@ -971,6 +1018,11 @@ begin
i2c_sda_i => fd0_sda_in,
fmc_present_n_i => fmc0_prsntm2c_n_i,
idelay_cal_o => fd0_tdc_start_iodelay_cal,
idelay_rst_o => fd0_tdc_start_iodelay_rst,
idelay_ce_o => fd0_tdc_start_iodelay_ce,
idelay_inc_o => fd0_tdc_start_iodelay_inc,
wb_adr_i => cnx_master_out(c_SLAVE_FD0).adr,
wb_dat_i => cnx_master_out(c_SLAVE_FD0).dat,
wb_dat_o => cnx_master_in(c_SLAVE_FD0).dat,
......@@ -1006,11 +1058,32 @@ begin
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => fd1_tdc_start, -- Buffer output
O => fd1_tdc_start_predelay, -- Buffer output
I => fd1_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fd1_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
);
cmp_fd_tdc_start_delay1 : IODELAY2
generic map (
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
DATA_RATE => "SDR"
)
port map (
IDATAIN => fd1_tdc_start_predelay,
DATAOUT2 => fd1_tdc_start,
INC => fd1_tdc_start_iodelay_inc,
CE => fd1_tdc_start_iodelay_ce,
RST => fd1_tdc_start_iodelay_rst,
CLK => dcm1_clk_ref_0,
ODATAIN => '0',
CAL => fd1_tdc_start_iodelay_cal,
T => '1',
IOCLK0 => dcm1_clk_ref_0,
IOCLK1 => '0'
);
U_DDR_PLL1 : fd_ddr_pll
port map (
RST => ddr1_pll_reset,
......@@ -1086,6 +1159,11 @@ begin
i2c_sda_i => fd1_sda_in,
fmc_present_n_i => fmc1_prsntm2c_n_i,
idelay_cal_o => fd1_tdc_start_iodelay_cal,
idelay_rst_o => fd1_tdc_start_iodelay_rst,
idelay_ce_o => fd1_tdc_start_iodelay_ce,
idelay_inc_o => fd1_tdc_start_iodelay_inc,
wb_adr_i => cnx_master_out(c_SLAVE_FD1).adr,
wb_dat_i => cnx_master_out(c_SLAVE_FD1).dat,
wb_dat_o => cnx_master_in(c_SLAVE_FD1).dat,
......
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