hdl: missing signal fix

9aef0922 · Tomasz Wlostowski · 5c08b95a · 9aef0922 · 9aef0922
Commit 9aef0922 authored Feb 26, 2012 by Tomasz Wlostowski
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Showing with 24 additions and 2 deletions

fine_delay_core.vhd hdl/rtl/fine_delay_core.vhd +1 -0

fine_delay_pkg.vhd hdl/rtl/fine_delay_pkg.vhd +23 -2

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--- a/hdl/rtl/fine_delay_core.vhd
+++ b/hdl/rtl/fine_delay_core.vhd
@@ -323,6 +323,7 @@ architecture rtl of fine_delay_core is
  signal dmtd_pattern : std_logic;
  signal calr_rd_ack, spllr_rd_ack : std_logic;
  signal csync_pps : std_logic;
+  signal tdc_cal_pulse : std_logic;
  
  
 begin  -- rtl

--- a/hdl/rtl/fine_delay_pkg.vhd
+++ b/hdl/rtl/fine_delay_pkg.vhd
@@ -10,7 +10,7 @@
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
-- Description: Main package
+-- Description: Main package.
 -------------------------------------------------------------------------------
 --
 -- Copyright (c) 2011 CERN / BE-CO-HT
@@ -48,15 +48,34 @@ use work.fd_channel_wbgen2_pkg.all;

 package fine_delay_pkg is

+  -----------------------------------------------------------------------------
+  -- User editable constants
+  -----------------------------------------------------------------------------
+
+  -- Timestamp field bits (if you change them, you must also change the WB files)
  constant c_TIMESTAMP_UTC_BITS         : integer := 40;
  constant c_TIMESTAMP_COARSE_BITS      : integer := 28;
  constant c_TIMESTAMP_FRAC_BITS        : integer := 12;
+
+  -- log2(Number of entries in the timestamp buffer)
  constant c_RING_BUFFER_SIZE_LOG2      : integer := 10;
+
+  -- Reference clock frequency in Hz
  constant c_REF_CLK_FREQ               : integer := 125000000;
+
+  -- System clock frequency in Hz
  constant c_SYS_CLK_FREQ               : integer := 62500000;
+
+  -- Reference clock period in picoseconds
  constant c_REF_CLK_PERIOD_PS          : integer := 8000;
+
+  -- Number of card outputs 
  constant c_FD_NUM_OUTPUTS             : integer := 4;
+
+  -- Number of reference clock cycles per one DDMTD calibration period
  constant c_FD_DMTD_CALIBRATION_PERIOD : integer := 125;
+
+  -- Calibration pulse width
  constant c_FD_DMTD_CALIBRATION_PWIDTH : integer := 3;

  type t_fd_timestamp is record
@@ -69,6 +88,9 @@ package fine_delay_pkg is
  type t_fd_timestamp_array is array (0 to c_FD_NUM_OUTPUTS-1) of t_fd_timestamp;


+  -------------------------------------------------------------------------------
+  -- Component declarations
+  -----------------------------------------------------------------------------  
  component fd_ts_adder
    generic (
      g_frac_bits    : integer := c_TIMESTAMP_FRAC_BITS;
@@ -149,7 +171,6 @@ package fine_delay_pkg is
      csync_coarse_i    : in  std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
      csync_utc_i       : in  std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
      csync_p1_i        : in  std_logic;
-      tdc_start_p1_o    : out std_logic;
      regs_i            : in  t_fd_main_out_registers;
      regs_o            : out t_fd_main_in_registers;
      dbg_o             : out std_logic_vector(3 downto 0));