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FMC DEL 1ns 4cha
Commit 982968c2 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: register dcr_enable bit to help with timing (#28)

parent ab8edc42
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Showing with 6 additions and 3 deletions
hdl/rtl/fd_delay_channel_driver.vhd
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...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2014-03-24 -- Last update: 2023-10-26
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -194,6 +194,7 @@ architecture behavioral of fd_delay_channel_driver is ...@@ -194,6 +194,7 @@ architecture behavioral of fd_delay_channel_driver is
signal tag_valid_d : std_logic_vector(4 downto 0); signal tag_valid_d : std_logic_vector(4 downto 0);
signal dcr_arm_d : std_logic_vector(4 downto 0); signal dcr_arm_d : std_logic_vector(4 downto 0);
signal dcr_en_d : std_logic;
signal regs_in : t_fd_channel_out_registers; signal regs_in : t_fd_channel_out_registers;
signal regs_out : t_fd_channel_in_registers; signal regs_out : t_fd_channel_in_registers;
...@@ -228,9 +229,11 @@ begin ...@@ -228,9 +229,11 @@ begin
if rst_n_ref_i = '0' then if rst_n_ref_i = '0' then
tag_valid_d <= (others => '0'); tag_valid_d <= (others => '0');
dcr_arm_d <= (others => '0'); dcr_arm_d <= (others => '0');
dcr_en_d <= '0';
else else
tag_valid_d <= tag_valid_d(tag_valid_d'length-2 downto 0) & tag_valid_i; tag_valid_d <= tag_valid_d(tag_valid_d'length-2 downto 0) & tag_valid_i;
dcr_arm_d <= dcr_arm_d(dcr_arm_d'length-2 downto 0) & regs_in.dcr_pg_arm_o; dcr_arm_d <= dcr_arm_d(dcr_arm_d'length-2 downto 0) & regs_in.dcr_pg_arm_o;
dcr_en_d <= regs_in.dcr_enable_o;
end if; end if;
end if; end if;
end process; end process;
...@@ -393,7 +396,7 @@ begin ...@@ -393,7 +396,7 @@ begin
p_match_hit_stage1 : process(clk_ref_i) p_match_hit_stage1 : process(clk_ref_i)
begin begin
if rising_edge(clk_ref_i) then if rising_edge(clk_ref_i) then
if rst_n_ref_i = '0' or regs_in.dcr_enable_o = '0' then if rst_n_ref_i = '0' or dcr_en_d = '0' then
hit_end <= '0'; hit_end <= '0';
hit_start <= '0'; hit_start <= '0';
hit_start_stage1 <= (others => '0'); hit_start_stage1 <= (others => '0');
...@@ -421,7 +424,7 @@ begin ...@@ -421,7 +424,7 @@ begin
p_fine_fsm : process(clk_ref_i) p_fine_fsm : process(clk_ref_i)
begin begin
if rising_edge(clk_ref_i) then if rising_edge(clk_ref_i) then
if rst_n_ref_i = '0' or regs_in.dcr_enable_o = '0' then if rst_n_ref_i = '0' or dcr_en_d = '0' then
state <= IDLE; state <= IDLE;
delay_load_o <= '0'; delay_load_o <= '0';
first_pulse <= '1'; first_pulse <= '1';
......
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