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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
7f430c0e
Commit
7f430c0e
authored
Oct 24, 2012
by
Tomasz Wlostowski
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hdl/rtl/fd_main_wishbone_slave: fix TS buffer interrupt polarity
parent
60df718d
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3 changed files
with
5 additions
and
21 deletions
+5
-21
fd_main_regs.html
hdl/rtl/doc/fd_main_regs.html
+1
-1
fd_main_wishbone_slave.vhd
hdl/rtl/fd_main_wishbone_slave.vhd
+3
-19
fd_main_wishbone_slave.wb
hdl/rtl/fd_main_wishbone_slave.wb
+1
-1
No files found.
hdl/rtl/doc/fd_main_regs.html
View file @
7f430c0e
...
...
@@ -12738,7 +12738,7 @@ TS_BUF_NOTEMPTY
<b>
Trigger:
</b>
</td>
<td
>
low
level
high
level
</td>
</tr>
</table>
...
...
hdl/rtl/fd_main_wishbone_slave.vhd
View file @
7f430c0e
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created :
Mon Jun 4 13:42:2
0 2012
-- Created :
Wed Oct 24 15:07:3
0 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
...
...
@@ -147,8 +147,6 @@ signal fd_main_calr_cal_pps_int : std_logic ;
signal
fd_main_calr_cal_pps_sync0
:
std_logic
;
signal
fd_main_calr_cal_pps_sync1
:
std_logic
;
signal
fd_main_calr_cal_dmtd_int
:
std_logic
;
signal
fd_main_calr_cal_dmtd_sync0
:
std_logic
;
signal
fd_main_calr_cal_dmtd_sync1
:
std_logic
;
signal
fd_main_calr_psel_int
:
std_logic_vector
(
3
downto
0
);
signal
fd_main_calr_psel_swb
:
std_logic
;
signal
fd_main_calr_psel_swb_delay
:
std_logic
;
...
...
@@ -1707,21 +1705,7 @@ begin
-- Produce DDMTD calibration pattern
-- synchronizer chain for field : Produce DDMTD calibration pattern (type RW/RO, clk_sys_i <-> clk_ref_i)
process
(
clk_ref_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
regs_o
.
calr_cal_dmtd_o
<=
'0'
;
fd_main_calr_cal_dmtd_sync0
<=
'0'
;
fd_main_calr_cal_dmtd_sync1
<=
'0'
;
elsif
rising_edge
(
clk_ref_i
)
then
fd_main_calr_cal_dmtd_sync0
<=
fd_main_calr_cal_dmtd_int
;
fd_main_calr_cal_dmtd_sync1
<=
fd_main_calr_cal_dmtd_sync0
;
regs_o
.
calr_cal_dmtd_o
<=
fd_main_calr_cal_dmtd_sync1
;
end
if
;
end
process
;
regs_o
.
calr_cal_dmtd_o
<=
fd_main_calr_cal_dmtd_int
;
-- Enable pulse generation
-- asynchronous std_logic_vector register : Enable pulse generation (type RW/RO, clk_ref_i <-> clk_sys_i)
process
(
clk_ref_i
,
rst_n_i
)
...
...
@@ -2047,7 +2031,7 @@ begin
eic_irq_controller_inst
:
wbgen2_eic
generic
map
(
g_num_interrupts
=>
3
,
g_irq00_mode
=>
2
,
g_irq00_mode
=>
3
,
g_irq01_mode
=>
0
,
g_irq02_mode
=>
0
,
g_irq03_mode
=>
0
,
...
...
hdl/rtl/fd_main_wishbone_slave.wb
View file @
7f430c0e
...
...
@@ -933,7 +933,7 @@ write 0: DMTD pattern generation disabled.";
irq {
name = "TS Buffer not empty.";
trigger = LEVEL_
0
;
trigger = LEVEL_
1
;
prefix = "ts_buf_notempty";
};
...
...
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