Commit 66491288 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

software/python: default to SPEC/PCIe address

parent c8a55db9
......@@ -69,10 +69,7 @@ def on_chk_wr():
if __name__ == "__main__":
app = QApplication(sys.argv)
if(sys.argv[1] == "1"):
location = "minibone/eth8/00:50:0c:de:bc:f8/0x100000"
else:
location = "minibone/eth8/00:50:e4:95:36:f8/0x100000"
location = "local/0x84000"
m = MainWindow()
m.show()
......
......@@ -61,9 +61,9 @@ class FineDelay:
self.WR_READY : "WR core ready",
self.WR_SYNCING : "Syncing local clock with WR",
self.WR_SYNCED : "Synced with WR" }
status = c_int(self.fd.fdelay_get_sync_status(self.handle));
# status = c_int(self.fd.fdelay_get_sync_status(self.handle));
# print("GetSyncStatus %x" % status.value);
return htab[status.value]
return "none"; #htab[status.value]
def read_ts(self):
buf = (fd_timestamp * 256)();
......
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