Main control registers of the particular output channel of the Fine Delay Core.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{ENABLE}
@tab @code{0} @tab
Enable channel
@item @code{1}
@tab R/W @tab
@code{MODE}
@tab @code{0} @tab
Delay mode select
@item @code{2}
@tab W/O @tab
@code{PG_ARM}
@tab @code{0} @tab
Pulse generator arm
@item @code{3}
@tab R/O @tab
@code{PG_TRIG}
@tab @code{X} @tab
Pulse generator triggered
@item @code{4}
@tab W/O @tab
@code{UPDATE}
@tab @code{0} @tab
Update Delay/Absoulte trigger time
@item @code{5}
@tab R/O @tab
@code{UPD_DONE}
@tab @code{X} @tab
Delay Update Done
@item @code{6}
@tab W/O @tab
@code{FORCE_DLY}
@tab @code{0} @tab
Force Calibration Delay
@item @code{7}
@tab R/W @tab
@code{NO_FINE}
@tab @code{0} @tab
Disable fine part update
@item @code{8}
@tab R/W @tab
@code{FORCE_HI}
@tab @code{0} @tab
Force Output High
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ENABLE} @tab write 0: channel is disabled. Output is driven LOW.@* write 1: channel is enabled. Output may produce pulses.
@item @code{MODE} @tab 0: Channel will work as a delay generator, producing delayed copies of pulses coming to the trigger input. Start/End registers shall contain delays of respectively, the rising and falling edge.@* 1: Channel will work as a programmable pulse generator - producing a pulse which begins and ends at absolute TAI times stored in Start/End registers.@* @b{Note:}@code{MODE} bit can be safely set only when the delay logic are disabled (i.e. when @code{DCR.ENABLE == 0})
@item @code{PG_ARM} @tab write 1: arms the pulse generator. @* write 0: no effect.@* @b{Note:}The values written to @code{[U/C/F]_START} and @code{[U/C/F]_END} must be bigger by at least 300 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much higher, as it's affected by the non-determinism of the operating system.
@item @code{PG_TRIG} @tab read 1: pulse generator has been triggered and produced a pulse@* read 0: pulse generator is busy or hasn't triggered yet
@item @code{UPDATE} @tab write 1: Starts the update procedure. The start and end times from @code{[U/C/F][START/END]} will be transferred in an atomic way to the internal delay/pulse generator registers.@* write 0: no effect.@* @b{Note}Care must be taken when updating the delay value - if the channel gets stuck due to invalid control values written, the only way to bring it back alive is to disable and re-enable it by toggling @code{DCR.ENABLE} bit.
@item @code{UPD_DONE} @tab read 1: The delays from @code{[U/C/F][START/END]} have been loaded into internal registers. Subsequent triggers will be delayed by the newly programmed value.@* read 0: update operation in progress
@item @code{FORCE_DLY} @tab Used in type 1 calibration.@* write 1: preloads the SY89295 delay line with the contents of FRR register.@* write 0: no effect
@item @code{NO_FINE} @tab write 1: disables updating of the fine part of the pulse delay to allow for producing faster signals (i.e. pulse width/spacing < 200 ns), at the cost of less accurate width/spacing control (multiple of 4 ns). @*write 0: normal operation. Pulse width/spacing must be at least 200 ns, width/spacing resolution is 10 ps.@*@b{Note:} A typical use case for @code{NO_FINE} bit is producing a 10 MHz clock.
@item @code{FORCE_HI} @tab write 1: Forces constant 1 on the output when the channel is disabled@* write 0: Forces constant 0 on the output when the channel is disabled@* Used for testing/calibration purposes.
@end multitable
@regsection @code{FRR} - Fine Range Register
Delay line tap setting at which the line generates an 8 ns (one cycle) longer delay than when set to 0. Used by type 1 calibration logic.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{9...0}
@tab R/W @tab
@code{FRR}
@tab @code{0} @tab
Fine range in SY89825 taps.
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{U_STARTH} - Pulse start time / offset (MSB TAI seconds)
TAI seconds (8 upper bits) part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab R/W @tab
@code{U_STARTH}
@tab @code{0} @tab
TAI seconds (MSB)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{U_STARTL} - Pulse start time / offset (LSB TAI seconds)
TAI seconds (32 lower bits) part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
Sub-second part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{27...0}
@tab R/W @tab
@code{C_START}
@tab @code{0} @tab
Reference clock cycles
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{F_START} - Pulse start time / offset (sub-cycle fine part)
Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{11...0}
@tab R/W @tab
@code{F_START}
@tab @code{0} @tab
Fractional part
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{U_ENDH} - Pulse end time / offset (MSB TAI seconds)
TAI seconds (8 upper bits) part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab R/W @tab
@code{U_ENDH}
@tab @code{0} @tab
TAI seconds (MSB)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{U_ENDL} - Pulse end time / offset (LSB TAI seconds)
TAI seconds (32 lower bits) part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{U_ENDL}
@tab @code{0} @tab
TAI seconds (LSB)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{C_END} - Pulse end time / offset (8 ns cycles)
Sub-second part of the pulse endabsolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{27...0}
@tab R/W @tab
@code{C_END}
@tab @code{0} @tab
Reference clock cycles
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{F_END} - Pulse end time / offset (sub-cycle fine part)
Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{11...0}
@tab R/W @tab
@code{F_END}
@tab @code{0} @tab
Fractional part
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{U_DELTA} - Pulse spacing (TAI seconds)
TAI seconds between rising edges of subsequent output pulses.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
Reference clock cycles between rising edges of subsequent output pulses.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{27...0}
@tab R/W @tab
@code{C_DELTA}
@tab @code{0} @tab
Reference clock cycles
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{F_DELTA} - Pulse spacing (sub-cycle fine part)
Sub-cycle part of spacing between rising edges of subsequent output pulses.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{11...0}
@tab R/W @tab
@code{F_DELTA}
@tab @code{0} @tab
Fractional part
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{RCR} - Repeat Count Register
Register controlling the number of output pulses to be generated upon reception of a trigger pulse or triggering the channel in PG mode.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{REP_CNT}
@tab @code{0} @tab
Repeat Count
@item @code{16}
@tab R/W @tab
@code{CONT}
@tab @code{0} @tab
Continuous Waveform Mode
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{CONT} @tab write 1: output will produce a contiguous square wave upon reception of trigger pulse. The generation can be aborted only disabling the channel (clearing @code{DCR.ENABLE})@* write 0: each trigger will produce @code{RCR.REP_CNT+1} pulses.
Timestamp Buffer Readout Fine/Channel/Sequence ID Register
@item @code{0x68} @tab
REG @tab
@code{I2CR} @tab
I2C bitbanged IO register
@item @code{0x6c} @tab
REG @tab
@code{TDER1} @tab
Test/Debug register 1
@item @code{0x70} @tab
REG @tab
@code{TDER2} @tab
Test/Debug register 1
@item @code{0x74} @tab
REG @tab
@code{TSBR_DEBUG} @tab
Timestamp Buffer Debug Values Register
@item @code{0x78} @tab
REG @tab
@code{TSBR_ADVANCE} @tab
Timestamp Buffer Advance Register
@item @code{0x80} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x84} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x88} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0x8c} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
@end multitable
@regsection @code{RSTR} - Reset Register
Controls software reset of the Fine Delay core and the mezzanine connected to it. Both reset lines are driven @* indepentently, there is also an unlock word provided to prevent resetting the board/core by accidentally accessing this register.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{RST_FMC}
@tab @code{0} @tab
State of the reset Line of the Mezzanine (EXT_RST_N pin)
@item @code{1}
@tab W/O @tab
@code{RST_CORE}
@tab @code{0} @tab
State of the reset of the Fine Delay Core
@item @code{31...16}
@tab W/O @tab
@code{LOCK}
@tab @code{0} @tab
Reset magic value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{RST_FMC} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation
@item @code{RST_CORE} @tab write 0: FD Core is held in reset@* write 1: Normal FD Core operation
@item @code{LOCK} @tab Protection field - the state of FMC and core lines will@* only be updated if LOCK is written with 0xdead together with the new state of the reset lines.
@end multitable
@regsection @code{IDR} - ID Register
Magic identification value (for detecting FD cores by the driver). Even though now enumeration is handled through SDB, but the register is kept for compatibility with older software.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{IDR}
@tab @code{X} @tab
ID Magic Value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IDR} @tab Equal to @code{0xf19ede1a}
@end multitable
@regsection @code{GCR} - Global Control Register
Common control bits used throughout the core.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{BYPASS}
@tab @code{0} @tab
Bypass Hardware TDC/Delay Controller
@item @code{1}
@tab R/W @tab
@code{INPUT_EN}
@tab @code{0} @tab
Enable trigger input
@item @code{2}
@tab R/O @tab
@code{DDR_LOCKED}
@tab @code{X} @tab
PLL Lock status
@item @code{3}
@tab R/O @tab
@code{FMC_PRESENT}
@tab @code{X} @tab
Mezzanine Present
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{BYPASS} @tab Descides who is in charge of the TDC and delay lines:@* write 0: TDC and delay lines are controlled by the HDL core (normal operation mode)@* write 1: TDC and delay lines controlled from the host via @code{TDR} and @code{TDCSR} registers (calibration and testing mode)
@item @code{INPUT_EN} @tab write 1: trigger input is enabled@* write 0: trigger input is disabled.@* @b{Note:} state of @code{INPUT_EN} is relevant only in normal operation mode (i.e. when @code{GCR.BYPASS} == 0). Warning! enabling the input in @code{INPUT_EN}@* does not mean it will be automatically enabled in the ACAM TDC - one must pre-program its registers first.
@item @code{DDR_LOCKED} @tab read 1: AD9516 and internal DDR PLLs are locked@* read 0: AD9516 or internal DDR PLL not (yet) locked
@item @code{FMC_PRESENT} @tab Mirrors the state of the FMC's PRSNT_L hardware pin: @* read 1: FMC card is present (@code{PRSNT_L == 0})@* read 0: no FMC card in the slot (@code{PRSNT_L == 1})
@end multitable
@regsection @code{TCR} - Timing Control Register
Controls time setting and White Rabbit/local time base selection.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{DMTD_STAT}
@tab @code{X} @tab
DMTD Clock Status
@item @code{1}
@tab R/W @tab
@code{WR_ENABLE}
@tab @code{0} @tab
WR Timing Enable
@item @code{2}
@tab R/O @tab
@code{WR_LOCKED}
@tab @code{X} @tab
WR Timing Locked
@item @code{3}
@tab R/O @tab
@code{WR_PRESENT}
@tab @code{X} @tab
WR Core Present
@item @code{4}
@tab R/O @tab
@code{WR_READY}
@tab @code{X} @tab
WR Core Time Ready
@item @code{5}
@tab R/O @tab
@code{WR_LINK}
@tab @code{X} @tab
WR Core Link Up
@item @code{6}
@tab W/O @tab
@code{CAP_TIME}
@tab @code{0} @tab
Capture Current Time
@item @code{7}
@tab W/O @tab
@code{SET_TIME}
@tab @code{0} @tab
Set Current Time
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{DMTD_STAT} @tab Status of the DMTD (helper) clock, used for DDMTD calibration purposes by the test suite.@* read 0: DMTD clock is not available or has been lost since last read operation of @code{TCR} register@* read 1: DMTD has been OK since previous read of @code{TCR} register
@item @code{WR_ENABLE} @tab Enables/disables WR synchronization.@* write 1: WR synchronization is enabled. Poll the @code{TCR.WR_LOCKED} bit to check if the WR Core is still locked.@* write 0: WR synchronization is disabled, the card is in free running mode.@* @b{Note:} enabling WR synchronization will cause a jump in the time base counter of the core. This may lead to lost pulses, therefore it is strongly@* recommended do disable the inputs/outputs before entering WR mode. When WR mode is disabled, the core will continue counting without a jump.
@item @code{WR_LOCKED} @tab Status of WR synchronization. @* read 0: local oscillator/time base is not locked to WR (or a transient delock event occured since last read of WR_TCR register).@* read 1: local oscillator is syntonized to WR and local timebase is aligned with WR time.
@item @code{WR_PRESENT} @tab Indicates whether we have a WR Core associated with this Fine Delay Core. Reflects the state@* of the @code{g_with_wr_core} generic HDL parameter. @* read 0: No WR Core present. Enabling WR will have no effect.@* read 1: WR Core available.
@item @code{WR_READY} @tab Indicates the status of synchronization of the associated WR core. Valid only if @code{TCR.WR_PRESENT} bit is set.@* read 0: WR Core is not synchronzied yet: there is no link, no PTP master in the network or synchronization is in progress.@* read 1: WR Core time is ready. User may enable WR reference by setting @code{TCR.WR_ENABLE} bit.@* @b{Note:} it is allowed to enable the WR mode even if @code{TCR.WR_READY} or @code{TCR.WR_LINK} bits are not set. Time base will@* be synced to WR as soon as the core gets correct PTP time from the master.
@item @code{WR_LINK} @tab Reflects the state of the WR Core's Ethernet link. Provided as an additional diagnostic feature.@* read 0: Ethernet link is down.@* read 1: Ethernet link is up.
@item @code{CAP_TIME} @tab Performs an atomic read of the core's current time.@* write 1: transfers the current value of seconds/cycles counters to @code{TM_xxx} registers.@* write 0: no effect.
@item @code{SET_TIME} @tab Sets internal time base counter to a given time in an atomic way:@* write 1: transfers the current value of @code{TM_x} to the timebase counters.@* write 0: no effect.@* @b{Note 1:} Internal time counters must be always initialized to a known value (e.g. zeroes), after every reset/power cycle.@* @b{Note 2:} Writing to @code{TCR.SET_TIME} while WR mode is active is forbidden. If you do so, prepare for unforeseen consequences.
@end multitable
@regsection @code{TM_SECH} - Time Register - TAI seconds (MSB)
Seconds counter, most significant part@* read: value of internal seconds counter taken upon last write to @code{TCR.CAP_TIME} bit.@* write: new value of seconds counter (loaded to the time base counter by writing @code{TCR.SET_TIME} bit)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab R/W @tab
@code{TM_SECH}
@tab @code{X} @tab
TAI seconds (MSB)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{TM_SECL} - Time Register - TAI seconds (LSB)
Seconds counter, least significant part@* read: value of internal seconds counter taken upon last write to @code{TCR.CAP_TIME} bit.@* write: new value of seconds counter (loaded to the time base counter by writing @code{TCR.SET_TIME} bit)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
Number of 125 MHz reference clock cycles from the beginning of the current second. @* read: value of cycles counter taken upon last write to @code{TCR.CAP_TIME} bit.@* write: new value of cycles counter (loaded to the time base counter by writing @code{TCR.SET_TIME} bit)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{27...0}
@tab R/W @tab
@code{TM_CYCLES}
@tab @code{X} @tab
Reference clock cycles (0...124999999)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{TDR} - Host-driven TDC Data Register.
Holds the 28-bit data word read from/to be written to the ACAM TDC, when the core is configured in bypass mode (@code{GCR.BYPASS == 1}).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
Allows controlling the TDC directly from the host (when @code{GCR.BYPASS == 1}).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{WRITE}
@tab @code{0} @tab
Write to TDC
@item @code{1}
@tab W/O @tab
@code{READ}
@tab @code{0} @tab
Read from TDC
@item @code{2}
@tab R/O @tab
@code{EMPTY}
@tab @code{X} @tab
Empty flag
@item @code{3}
@tab W/O @tab
@code{STOP_EN}
@tab @code{0} @tab
Stop enable
@item @code{4}
@tab W/O @tab
@code{START_DIS}
@tab @code{0} @tab
Start disable
@item @code{5}
@tab W/O @tab
@code{START_EN}
@tab @code{0} @tab
Start enable
@item @code{6}
@tab W/O @tab
@code{STOP_DIS}
@tab @code{0} @tab
Stop disable
@item @code{7}
@tab W/O @tab
@code{ALUTRIG}
@tab @code{0} @tab
Pulse <code>Alutrigger</code> line
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{WRITE} @tab Writes the data word from @code{TDR}register to the ACAM TDC.@* write 1: write the data word programmed in @code{TDR} TDR register to the TDC. The TDC address must be set via the SPI I/O expander.@* write 0: no effect.
@item @code{READ} @tab Reads a data word from the TDC and puts it in @code{TDR} register.@* write 1: read a data word from the TDC. The read word will be put in the @code{TDR} register. The TDC address must be set via the SPI I/O expander.@* write 0: no effect.
@item @code{EMPTY} @tab Raw status of the @code{EF} (FIFO empty) pin of the TDC.@* read 0: there is one (or more) pending timestamp(s) in the ACAM's internal FIFO.@* read 1: the internal TDC FIFO is empty (no timestamps to read).
@item @code{STOP_EN} @tab Controls the @code{StopDis} input of the TDC.@* write 1: enables the TDC stop input.@* write 0: no effect.
@item @code{START_DIS} @tab Controls the @code{StartDis} input of the TDC.@* write 1: disables the TDC start input.@* write 0: no effect.
@item @code{START_EN} @tab Controls the @code{StartDis} input of the TDC.@* write 1: enables the TDC start input.@* write 0: no effect.
@item @code{STOP_DIS} @tab Controls the @code{StopDis} input of the TDC.@* write 1: disables the TDC stop input.@* write 0: no effect.
@item @code{ALUTRIG} @tab Controls the TDC's @code{Alutrigger} line. Depending on the TDC's configuration, it can be used as a reset/FIFO clear/trigger signal.@* write 1: generates a pulse ACAM's @code{Alutrigger} line@* write 0: no effect.
@end multitable
@regsection @code{CALR} - Calibration register
Controls calibration logic.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{CAL_PULSE}
@tab @code{0} @tab
Generate calibration pulses (type 1 calibration)
@item @code{1}
@tab R/W @tab
@code{CAL_PPS}
@tab @code{0} @tab
PPS Calibration output enable.
@item @code{2}
@tab R/W @tab
@code{CAL_DMTD}
@tab @code{0} @tab
Produce DDMTD calibration pattern (type 2 calibration)
@item @code{6...3}
@tab R/W @tab
@code{PSEL}
@tab @code{0} @tab
Calibration pulse output select/mask
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{CAL_PULSE} @tab Triggers generation of a calibration pulse on selected channels. Used to determine the exact 4/8ns setting tap of the fine delay line.@* write 1: Immediately generates a single calibration pulse on the TDC start input and the output channels selected in the PSEL field.@* write 0: no effect.@* @b{Note:} In order for the pulse to be tagged by the TDC, it must be driven in the BYPASS mode and properly configured (I-mode, see driver/test program).
@item @code{CAL_PPS} @tab Drives the TDC stop input with a PPS signal synchronous to the FD core's timebase:@* write 1: Feeds TDC input with internally generated PPS signal.@* write 0: PPS generation disabled.@* @b{Note:} Input multiplexer must be configured to drive the TDC trigger from the FPGA calibration output instead of the trigger input.
@item @code{CAL_DMTD} @tab Controls DDMTD test pattern generation:@* write 1: Enables DMTD test pattern on the TDC input and DDMTD sampling clock for the calibration flip-flops.@* write 0: DMTD pattern generation disabled.@* @b{Note:} Input multiplexer must be configured to drive the TDC trigger from the FPGA calibration output instead of the trigger input.
@item @code{PSEL} @tab 1: enable generation of type 1 calibration pulses (@code{CALR.CAL_PULSE}) on the output corresponding to the written bit@* 0: disable pulse generation for the corresponding output
@end multitable
@regsection @code{DMTR_IN} - DMTD Input Tag Register
Provides the DDMTD tag value for the input channel (type 2 calibration).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{30...0}
@tab R/O @tab
@code{TAG}
@tab @code{X} @tab
DMTD Tag
@item @code{31}
@tab R/O @tab
@code{RDY}
@tab @code{X} @tab
DMTD Tag Ready
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{TAG} @tab The tag value.
@item @code{RDY} @tab Tag ready flag (clear-on-read):@* 1: a new DDMTD tag is available.@* 0: tag not ready yet.
@end multitable
@regsection @code{DMTR_OUT} - DMTD Output Tag Register
Provides the DDMTD tag value for a selected output channel (type 2 calibration).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{30...0}
@tab R/O @tab
@code{TAG}
@tab @code{X} @tab
DMTD Tag
@item @code{31}
@tab R/O @tab
@code{RDY}
@tab @code{X} @tab
DMTD Tag Ready
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{TAG} @tab The tag value.
@item @code{RDY} @tab Tag ready flag (clear-on-read):@* 1: a new DDMTD tag is available.@* 0: tag not ready yet.
Scaling factor between the FD's internal time scale and the ACAM's format. Used only in normal operating mode (@code{GCR.BYPASS == 0}).@* Formula (for G-Mode): @code{ADFSR = round(2097.152 * ACAM_bin_size [ps])}
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{17...0}
@tab R/W @tab
@code{ADSFR}
@tab @code{0} @tab
ADFSR Value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{ATMCR} - Acam Timestamp Merging Control Register
Controls merging of fine timestamps prouced by Acam with coarse timestamps obtained by the FPGA. See developers' manual for explanation.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
ACAM timestamp start offset. Value that gets subtracted from ACAM's timestamps (due to ACAM's ALU architecture that does not support negative numbers). See developers' manual for explanation.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{22...0}
@tab R/W @tab
@code{OFFSET}
@tab @code{0} @tab
Start Offset
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{IECRAW} - Raw Input Events Counter Register
TDC debugging & statistics register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{IECRAW}
@tab @code{X} @tab
Number of raw events.
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IECRAW} @tab Number of all input pulses detected by the timestamper.
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{RST_STAT}
@tab @code{0} @tab
Reset stats
@item @code{8...1}
@tab R/O @tab
@code{PDELAY}
@tab @code{X} @tab
Processing delay
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{RST_STAT} @tab Write 1: resets the delay/pulse count counters (@code{IECRAW}, @code{IECTAG} and @code{IEPD_WDELAY})@* write 0: no effect
@item @code{PDELAY} @tab Worst-case delay between the input event and the generation of its timestamp. Expressed as a number of 125 MHz clock cycles.
@end multitable
@regsection @code{SCR} - SPI Control Register
Single control register for the SPI Controller, allowing for atomic updates of the DAC, GPIO and PLL.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{23...0}
@tab R/W @tab
@code{DATA}
@tab @code{X} @tab
Data
@item @code{24}
@tab R/W @tab
@code{SEL_DAC}
@tab @code{0} @tab
Select DAC
@item @code{25}
@tab R/W @tab
@code{SEL_PLL}
@tab @code{0} @tab
Select PLL
@item @code{26}
@tab R/W @tab
@code{SEL_GPIO}
@tab @code{0} @tab
Select GPIO
@item @code{27}
@tab R/O @tab
@code{READY}
@tab @code{X} @tab
Ready flag
@item @code{28}
@tab R/W @tab
@code{CPOL}
@tab @code{0} @tab
Clock Polarity
@item @code{29}
@tab W/O @tab
@code{START}
@tab @code{0} @tab
Transfer Start
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{DATA} @tab Data to be read/written from/to the SPI bus
@item @code{SEL_DAC} @tab write 1: selects the DAC as the target peripheral of the transfer@* write 0: no effect
@item @code{SEL_PLL} @tab write 1: selects the AD9516 PLL as the target peripheral of the transfer@* write 0: no effect
@item @code{SEL_GPIO} @tab write 1: selects the MCP23S17 GPIO as the target peripheral of the transfer@* write 0: no effect
@item @code{READY} @tab read 0: SPI controller is busy performing a transfer@* read 1: SPI controller has finished its previous transfer. Read-back data is available in @code{SCR.DATA}
@item @code{CPOL} @tab 0: SPI clock is not inverted (data valid on rising edge)@* 1: SPI clock is inverted (data valid on falling edge)
@item @code{START} @tab write 1: Starts SPI transfer from/to the selected peripheral@* write 0: no effect
Provides the momentary value of the internal clock rate counter. Can be used in conjunction with the DAC to roughly syntonize the card's reference clock with a clock coming from an external master installed in the same host (e.g. a CTRV/CTRP) in a software-only way or to measure tuning range of the local VCXO.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{RCRR}
@tab @code{X} @tab
Frequency
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{RCRR} @tab Reference clock frequency, in Hz
@end multitable
@regsection @code{TSBCR} - Timestamp Buffer Control Register
Controls timestamp readout from the core's circular buffer
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab R/W @tab
@code{CHAN_MASK}
@tab @code{0} @tab
Channel Mask
@item @code{5}
@tab R/W @tab
@code{ENABLE}
@tab @code{0} @tab
Buffer enable
@item @code{6}
@tab W/O @tab
@code{PURGE}
@tab @code{0} @tab
Buffer purge
@item @code{7}
@tab W/O @tab
@code{RST_SEQ}
@tab @code{0} @tab
Reset timestamp sequence number
@item @code{8}
@tab R/O @tab
@code{FULL}
@tab @code{X} @tab
Buffer full
@item @code{9}
@tab R/O @tab
@code{EMPTY}
@tab @code{X} @tab
Buffer empty
@item @code{21...10}
@tab R/O @tab
@code{COUNT}
@tab @code{X} @tab
Buffer entries count
@item @code{22}
@tab R/W @tab
@code{RAW}
@tab @code{0} @tab
RAW readout mode enable
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{CHAN_MASK} @tab Selects which channels' time tags shall be written to the buffer. @* bit @code{0}: TDC input@* bits @code{1..4}: = Delay outputs
@item @code{ENABLE} @tab Enables/disables timestamp readout:@* 1: timestamp buffer is enabled. Readout is possible.@* 0: timestamp buffer is disabled. Timestamps are processed (if set in delay mode), but discarded for readout.
@item @code{RST_SEQ} @tab write 1: reset timestamp sequence number counter@* write 0: no effect
@item @code{FULL} @tab read 1: buffer is full. Old timestamps (at the end of the buffer) will be discarded when new ones will come
@item @code{EMPTY} @tab read 1: buffer is empty
@item @code{COUNT} @tab Number of timestamps currently stored in the readout buffer
@item @code{RAW} @tab Enables raw timestamp readout mode (i.e. bypassing postprocessing). Used only for debugging purposes.@* write 1: enable raw mode@* write 0: disable raw mode (normal operation)
Controls the behaviour of the core's readout interrupt (coalescing).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{9...0}
@tab R/W @tab
@code{TIMEOUT}
@tab @code{0} @tab
IRQ timeout [milliseconds]
@item @code{21...10}
@tab R/W @tab
@code{THRESHOLD}
@tab @code{0} @tab
Interrupt threshold
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{TIMEOUT} @tab The IRQ line will be asserted after @code{TSBIR.TIMEOUT} milliseconds even if the amount of data in the buffer is below @code{TSBIR.THRESHOLD}.
@item @code{THRESHOLD} @tab Minimum number of samples (timestamps) in the buffer that immediately triggers an interrupt.
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{TS_BUF_NOTEMPTY}
@tab @code{X} @tab
Timestamp Buffer interrupt.
@item @code{1}
@tab R/O @tab
@code{DMTD_SPLL}
@tab @code{X} @tab
DMTD SoftPLL interrupt
@item @code{2}
@tab R/O @tab
@code{SYNC_STATUS}
@tab @code{X} @tab
Sync Status Changed
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ts_buf_notempty} @tab read 1: interrupt 'Timestamp Buffer interrupt.' is enabled@*read 0: interrupt 'Timestamp Buffer interrupt.' is disabled
@item @code{dmtd_spll} @tab read 1: interrupt 'DMTD SoftPLL interrupt' is enabled@*read 0: interrupt 'DMTD SoftPLL interrupt' is disabled
@item @code{sync_status} @tab read 1: interrupt 'Sync Status Changed' is enabled@*read 0: interrupt 'Sync Status Changed' is disabled
@end multitable
@regsection @code{EIC_ISR} - Interrupt status register
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TS_BUF_NOTEMPTY}
@tab @code{X} @tab
Timestamp Buffer interrupt.
@item @code{1}
@tab R/W @tab
@code{DMTD_SPLL}
@tab @code{X} @tab
DMTD SoftPLL interrupt
@item @code{2}
@tab R/W @tab
@code{SYNC_STATUS}
@tab @code{X} @tab
Sync Status Changed
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ts_buf_notempty} @tab read 1: interrupt 'Timestamp Buffer interrupt.' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'Timestamp Buffer interrupt.'@*write 0: no effect
@item @code{dmtd_spll} @tab read 1: interrupt 'DMTD SoftPLL interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'DMTD SoftPLL interrupt'@*write 0: no effect
@item @code{sync_status} @tab read 1: interrupt 'Sync Status Changed' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'Sync Status Changed'@*write 0: no effect
<br>0: channel is disabled<br> 1: channel is enabled
<li><b>
MODE
</b>[<i>read/write</i>]: Delay mode select
<br>0: Channel will work as a delay generator, producing delayed copies of pulses comming to the trigger input<br>1: Channel will work as a programmable pulse generator - producing a pulse which begins at UTC time [U_START, C_START, F_START] and ends at [U_END, C_END, F_END].<br><b>Warning:</b> MODE_DLY bit can be safely set only when the TDC and the delay logic are disabled (i.e. when GCR.BYPASS = 1)
<li><b>
PG_ARM
</b>[<i>write-only</i>]: Pulse generator arm
<br>write 1: arms the pulse generator. <br> write 0: no effect.<br> Note that the time written to [U/C/F]START must be bigger by at least 200 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much bigger, as it's affected by the non-determinism of the operating system.
<li><b>
PG_TRIG
</b>[<i>read-only</i>]: Pulse generator triggered
<br>read 1: pulse generator has been triggered and produced a pulse<br> read 0: pulse generator is busy or hasn't triggered yet
<li><b>
UPDATE
</b>[<i>write-only</i>]: Start Delay Update
<br>write 1: Starts delay update procedure. The start and end times from [U/C/F][START/END] will be transferred in an atomic way to the internal delay/pulse generator registers<br> write 0: no effect.
<li><b>
UPD_DONE
</b>[<i>read-only</i>]: Delay Update Done
<br>read 1: The delays from [U/C/F][START/END] have been loaded into internal registers<br> read 0: update operation in progress
<li><b>
FORCE_DLY
</b>[<i>write-only</i>]: Force Calibration Delay
<br>write 1: preloads the delay line with the contents of FRR register. Used for self-calibration purposes.<br> write 0: no effect
<li><b>
NO_FINE
</b>[<i>read/write</i>]: Disable Fine Part update
<br>write 1: disables updating of the fine part of the pulse delay to allow for producing faster signals (i.e. pulse width/spacing <200ns),atthecostoflessaccuratewidth/spacingcontrol(multipleof4ms).<br>write 0: normal operation. Pulse width/spacing must be at least 200 ns.
<li><b>
FORCE_HI
</b>[<i>read/write</i>]: Force Output High
<br>write 1: Forces constant 1 on the output when the channel is disabled<br> write 0: Forces constant 0 on the output when the channel is disabled<br> Used for testing/calibration purposes.
</ul>
<aname="FRR"></a>
<h3><aname="sect_3_2">3.2. Fine Range Register</a></h3>
<tablecellpadding=0cellspacing=0border=0>
<tr>
<td>
<b>HW prefix: </b>
</td>
<tdclass="td_code">
fd_channel_frr
</td>
</tr>
<tr>
<td>
<b>HW address: </b>
</td>
<tdclass="td_code">
0x1
</td>
</tr>
<tr>
<td>
<b>C prefix: </b>
</td>
<tdclass="td_code">
FRR
</td>
</tr>
<tr>
<td>
<b>C offset: </b>
</td>
<tdclass="td_code">
0x4
</td>
</tr>
</table>
<p>
Delay line tap setting at which the line generates an 8 ns (one cycle) longer delay than when set to 0.
<h3><aname="sect_3_5">3.5. Pulse start time / offset (8 ns cycles)</a></h3>
<tablecellpadding=0cellspacing=0border=0>
<tr>
<td>
<b>HW prefix: </b>
</td>
<tdclass="td_code">
fd_channel_c_start
</td>
</tr>
<tr>
<td>
<b>HW address: </b>
</td>
<tdclass="td_code">
0x4
</td>
</tr>
<tr>
<td>
<b>C prefix: </b>
</td>
<tdclass="td_code">
C_START
</td>
</tr>
<tr>
<td>
<b>C offset: </b>
</td>
<tdclass="td_code">
0x10
</td>
</tr>
</table>
<p>
Sub-second part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.
<h3><aname="sect_3_6">3.6. Pulse start time / offset (sub-cycle fine part)</a></h3>
<tablecellpadding=0cellspacing=0border=0>
<tr>
<td>
<b>HW prefix: </b>
</td>
<tdclass="td_code">
fd_channel_f_start
</td>
</tr>
<tr>
<td>
<b>HW address: </b>
</td>
<tdclass="td_code">
0x5
</td>
</tr>
<tr>
<td>
<b>C prefix: </b>
</td>
<tdclass="td_code">
F_START
</td>
</tr>
<tr>
<td>
<b>C offset: </b>
</td>
<tdclass="td_code">
0x14
</td>
</tr>
</table>
<p>
Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8ns>: 0 = 0 ps, 4095 = 7999 ps.
<h3><aname="sect_3_9">3.9. Pulse end time / offset (8 ns cycles)</a></h3>
<tablecellpadding=0cellspacing=0border=0>
<tr>
<td>
<b>HW prefix: </b>
</td>
<tdclass="td_code">
fd_channel_c_end
</td>
</tr>
<tr>
<td>
<b>HW address: </b>
</td>
<tdclass="td_code">
0x8
</td>
</tr>
<tr>
<td>
<b>C prefix: </b>
</td>
<tdclass="td_code">
C_END
</td>
</tr>
<tr>
<td>
<b>C offset: </b>
</td>
<tdclass="td_code">
0x20
</td>
</tr>
</table>
<p>
Sub-second part of the pulse endabsolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.
<h3><aname="sect_3_10">3.10. Pulse end time / offset (sub-cycle fine part)</a></h3>
<tablecellpadding=0cellspacing=0border=0>
<tr>
<td>
<b>HW prefix: </b>
</td>
<tdclass="td_code">
fd_channel_f_end
</td>
</tr>
<tr>
<td>
<b>HW address: </b>
</td>
<tdclass="td_code">
0x9
</td>
</tr>
<tr>
<td>
<b>C prefix: </b>
</td>
<tdclass="td_code">
F_END
</td>
</tr>
<tr>
<td>
<b>C offset: </b>
</td>
<tdclass="td_code">
0x24
</td>
</tr>
</table>
<p>
Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8ns>: 0 = 0 ps, 4095 = 7999 ps.
<br>write 1: output will produce a contiguous square wave upon receptio of trigger pulse. The generation can be aborted by disabling the channel (DCRx.ENABLE = 0)<br> write 0: output will produce trains of REP_CNT+1 pulses.
description = "Main control registers of the particular output channel of the Fine Delay Core.";
prefix = "DCR";
align = 8;
field {
name = "Enable channel";
prefix = "ENABLE";
description = "0: channel is disabled\
1: channel is enabled";
description = "write 0: channel is disabled. Output is driven LOW.\
write 1: channel is enabled. Output may produce pulses.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
...
...
@@ -65,9 +66,9 @@ peripheral {
field {
name = "Delay mode select";
prefix = "MODE";
description = "0: Channel will work as a delay generator, producing delayed copies of pulses comming to the trigger input\
1: Channel will work as a programmable pulse generator - producing a pulse which begins at UTC time [U_START, C_START, F_START] and ends at [U_END, C_END, F_END].\
<b>Warning:</b> MODE_DLY bit can be safely set only when the TDC and the delay logic are disabled (i.e. when GCR.BYPASS = 1)";
description = "0: Channel will work as a delay generator, producing delayed copies of pulses coming to the trigger input. Start/End registers shall contain delays of respectively, the rising and falling edge.\
1: Channel will work as a programmable pulse generator - producing a pulse which begins and ends at absolute TAI times stored in Start/End registers.\
<b>Note:</b> <code>MODE</code> bit can be safely set only when the delay logic are disabled (i.e. when <code>DCR.ENABLE == 0</code>)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
...
...
@@ -78,7 +79,7 @@ peripheral {
prefix = "PG_ARM";
description = "write 1: arms the pulse generator. \
write 0: no effect.\
Note that the time written to [U/C/F]START must be bigger by at least 200 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much bigger, as it's affected by the non-determinism of the operating system.";
<b>Note:</b> The values written to <code>[U/C/F]_START</code> and <code>[U/C/F]_END</code> must be bigger by at least 300 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much higher, as it's affected by the non-determinism of the operating system.";
type = MONOSTABLE;
clock = "clk_ref_i";
};
...
...
@@ -95,18 +96,19 @@ peripheral {
};
field {
name = "Start Delay Update";
name = "Update delay/absolute trigger time";
prefix = "UPDATE";
description = "write 1: Starts delay update procedure. The start and end times from [U/C/F][START/END] will be transferred in an atomic way to the internal delay/pulse generator registers\
write 0: no effect.";
description = "write 1: Starts the update procedure. The start and end times from <code>[U/C/F][START/END]</code> will be transferred in an atomic way to the internal delay/pulse generator registers.\
write 0: no effect.\
<b>Note:</b> Care must be taken when updating the delay value - if the channel gets stuck due to invalid control values written, the only way to bring it back alive is to disable and re-enable it by toggling <code>DCR.ENABLE</code> bit.";
type = MONOSTABLE;
clock = "clk_ref_i";
};
field {
name = "Delay Update Done";
name = "Delay update done flag";
prefix = "UPD_DONE";
description = "read 1: The delays from [U/C/F][START/END] have been loaded into internal registers\
description = "read 1: the delays from <code>[U/C/F][START/END]</code> have been loaded into internal registers. Subsequent triggers will be delayed by the newly programmed value.\
read 0: update operation in progress";
type = BIT;
access_bus = READ_ONLY;
...
...
@@ -115,9 +117,10 @@ peripheral {
};
field {
name = "Force Calibration Delay";
name = "Force calibration delay";
prefix = "FORCE_DLY";
description = "write 1: preloads the delay line with the contents of FRR register. Used for self-calibration purposes.\
description = "Used in type 1 calibration.\
write 1: preloads the SY89295 delay line with the contents of FRR register.\
write 0: no effect";
type = MONOSTABLE;
...
...
@@ -126,10 +129,11 @@ peripheral {
field {
name = "Disable Fine Part update";
name = "Disable fine part update";
prefix = "NO_FINE";
description = "write 1: disables updating of the fine part of the pulse delay to allow for producing faster signals (i.e. pulse width/spacing < 200 ns), at the cost of less accurate width/spacing control (multiple of 4 ms). \
write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
description = "write 1: disables updating of the fine part of the pulse delay to allow for producing faster signals (i.e. pulse width/spacing < 200 ns), at the cost of less accurate width/spacing control (multiple of 4 ns). \
write 0: normal operation. Pulse width/spacing must be at least 200 ns, width/spacing resolution is 10 ps.\
<b>Note:</b> A typical use case for <code>NO_FINE</code> bit is producing a 10 MHz clock.";
type = BIT;
access_bus = READ_WRITE;
...
...
@@ -137,10 +141,10 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
};
field {
name = "Force Output High";
name = "Force output high";
prefix = "FORCE_HI";
description = "write 1: Forces constant 1 on the output when the channel is disabled\
write 0: Forces constant 0 on the output when the channel is disabled\
description = "write 1: forces constant 1 on the output when the channel is disabled\
write 0: forces constant 0 on the output when the channel is disabled\
Used for testing/calibration purposes.";
type = BIT;
...
...
@@ -154,10 +158,10 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
reg {
name = "Fine Range Register";
prefix = "FRR";
description = "Delay line tap setting at which the line generates an 8 ns (one cycle) longer delay than when set to 0.";
description = "Delay line tap setting at which the line generates an 8 ns (one cycle) longer delay than when set to 0. Used by type 1 calibration logic.";
field {
name = "Fine Range";
name = "Fine range in SY89825 taps.";
size = 10;
type = SLV;
access_bus = READ_WRITE;
...
...
@@ -211,9 +215,9 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
};
reg {
name = "Pulse start time / offset (sub-cycle fine part)";
name = "Pulse start time / offset (fine part)";
prefix = "F_START";
description = "Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
description = "Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).";
field {
name = "Fractional part";
...
...
@@ -258,7 +262,7 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
reg {
name = "Pulse end time / offset (8 ns cycles)";
prefix = "C_END";
description = "Sub-second part of the pulse endabsolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
description = "Sub-second part of the pulse endabsolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
field {
name = "Reference clock cycles";
...
...
@@ -270,9 +274,9 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
};
reg {
name = "Pulse end time / offset (sub-cycle fine part)";
name = "Pulse end time / offset (fine part)";
prefix = "F_END";
description = "Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
description = "Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). ";
field {
name = "Fractional part";
...
...
@@ -289,7 +293,7 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
reg {
name = "Pulse spacing (TAI seconds)";
prefix = "U_DELTA";
description = "TAI seconds between rising edges of subsequent output pulses.";
description = "TAI seconds between the rising edges of subsequent output pulses.";
field {
name = "TAI seconds";
...
...
@@ -303,7 +307,7 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
reg {
name = "Pulse spacing (8 ns cycles)";
prefix = "C_DELTA";
description = "Reference clock cycles between rising edges of subsequent output pulses.";
description = "Reference clock cycles between the rising edges of subsequent output pulses.";
field {
name = "Reference clock cycles";
...
...
@@ -315,9 +319,9 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
};
reg {
name = "Pulse spacing (sub-cycle fine part)";
name = "Pulse spacing (fine part)";
prefix = "F_DELTA";
description = "Sub-cycle part of spacing between rising edges of subsequent output pulses.";
description = "Sub-cycle part of spacing between the rising edges of subsequent output pulses.";
field {
name = "Fractional part";
...
...
@@ -331,11 +335,11 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
reg {
name = "Repeat Count Register";
prefix = "RCR";
description = "Register controlling the number of output pulses to be generated upon reception of a trigger pulse.";
description = "Register controlling the number of output pulses to be generated upon reception of a trigger pulse or triggering the channel in PG mode.";
description = "Equal to desired number of pulses minus 1 (0 = 1 pulse, 0xffff = 65536 pulses)";
prefix = "REP_CNT";
size = 16;
type = SLV;
...
...
@@ -346,8 +350,8 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
field {
name = "Continuous Waveform Mode";
prefix = "CONT";
description = "write 1: output will produce a contiguous square wave upon receptio of trigger pulse. The generation can be aborted by disabling the channel (DCRx.ENABLE = 0)\
write 0: output will produce trains of REP_CNT+1 pulses.";
description = "write 1: output will produce a contiguous square wave upon reception of trigger pulse. The generation can be aborted only disabling the channel (clearing <code>DCR.ENABLE</code>)\
write 0: each trigger will produce <code>RCR.REP_CNT+1</code> pulses.";
description = "Controls software reset of the Fine Delay core and the mezzanine connected to it. Both reset lines are driven indepentently, there is also an unlock word provided to prevent resetting the board/core by accidentally accessing this register.";
field {
name = "State of the reset Line of the FMC Card";
name = "State of the reset Line of the Mezzanine (EXT_RST_N pin)";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation";
type = PASS_THROUGH;
...
...
@@ -59,7 +60,7 @@ peripheral {
};
field {
name = "State of the reset of the Fine Delay HDL Core";
name = "State of the reset of the Fine Delay Core";
description = "write 0: FD Core is held in reset\
write 1: Normal FD Core operation";
type = PASS_THROUGH;
...
...
@@ -69,8 +70,8 @@ peripheral {
field {
name = "Reset magic value";
description = "Protection field - the state of RST_FMC/RST_CORE lines will\
only be updated if LOCK is written with 0xdead together with the new state of the reset lines.";
description = "Protection field - the state of FMC and core lines will\
only be updated if <code>LOCK</code> is written with 0xdead together with the new state of the reset lines.";
type = PASS_THROUGH;
prefix = "LOCK";
align = 16;
...
...
@@ -80,12 +81,12 @@ peripheral {
reg {
name = "ID Register";
description = "Magic identification value (for detecting FD cores by the driver). Now the enumeration is handled through SDB, but the register is kept for compatibility with older software.";
description = "Magic identification value (for detecting FD cores by the driver). Even though now enumeration is handled through SDB, the <code>IDR</code> register is kept for compatibility with older software.";
prefix = "IDR";
field {
name = "ID Magic Value";
description = "Always 0xf19ede1a";
description = "Equal to <code>0xf19ede1a</code>";
size = 32;
type = CONSTANT;
value = 0xf19ede1a;
...
...
@@ -100,11 +101,11 @@ peripheral {
field {
clock = "clk_ref_i";
name = "Bypass Hardware TDC/Delay Controller";
name = "Bypass hardware TDC controller";
prefix = "BYPASS";
description = "Descides who is in charge of the TDC and delay lines:\
write 0: TDC and delay lines are controlled by the HDL core (normal operation)\
write 1: TDC and delay lines controlled from the host (calibration and testing)";
write 0: TDC and delay lines are controlled by the HDL core (normal operation mode)\
write 1: TDC and delay lines controlled from the host via <code>TDR</code> and <code>TDCSR</code> registers (calibration and testing mode)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
...
...
@@ -116,7 +117,8 @@ peripheral {
name = "Enable trigger input";
description = "write 1: trigger input is enabled\
write 0: trigger input is disabled.\
Note: state of INPUT_EN is relevant only in normal operation mode (i.e. when GCR.BYPASS == 0).";
<b>Note 1:</b> state of <code>INPUT_EN</code> is relevant only in normal operation mode (i.e. when <code>GCR.BYPASS</code> == 0). \
<b>Note 2:</b> enabling the input in <code>INPUT_EN</code> does not mean it will be automatically enabled in the ACAM TDC - one must pre-program its registers first.";
prefix = "INPUT_EN";
type = BIT;
access_bus = READ_WRITE;
...
...
@@ -125,9 +127,9 @@ peripheral {
field {
name = "PLL Locked";
description = "read 1: AD9516 and internal DDR PLLs locked\
read 0: PLL(s) not locked";
name = "PLL lock status";
description = "read 1: AD9516 and internal DDR PLLs are locked\
read 0: AD9516 or internal DDR PLL not (yet) locked";
write 1: WR synchronization is enabled. Poll the WR_LOCKED bit to check if the WR Core is still locked.\
write 1: WR synchronization is enabled. Poll the <code>TCR.WR_LOCKED</code> bit to check if the WR Core is still locked.\
write 0: WR synchronization is disabled, the card is in free running mode.\
Note: enabling WR synchronization will cause a jump in the time base counter of the core. This may lead to lost pulses, therefore it is strongly\
recommended do disable the trigger input before entering WR mode. When WR mode is disabled, the core will continue with the last known WR time, counted with the local oscillator (no jump).";
<b>Note:</b> enabling WR synchronization will cause a jump in the time base counter of the core. This may lead to lost pulses, therefore it is strongly recommended do disable the inputs/outputs before entering WR mode. When WR mode is disabled, the core will continue counting without a jump.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
...
...
@@ -184,8 +183,8 @@ peripheral {
name = "WR Timing Locked";
prefix = "WR_LOCKED";
description = "Status of WR synchronization. \
read 0: local oscillator/time base is not locked to WR (or has lost its lock since last read of WR_TCR register)\
read 1: local oscillator is syntonized to WR and local timebase is aligned with WR time.";
read 0: local oscillator/time base is not locked to WR (or a transient delock event occured since last read of <code>TCR</code> register).\
read 1: local oscillator is syntonized to WR and local timebase is aligned with WR time.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
...
...
@@ -194,8 +193,7 @@ peripheral {
field {
name = "WR Core Present";
prefix = "WR_PRESENT";
description = "Indicates whether we have a WR Core associated with this Fine Delay Core. Reflects the state\
of 'g_with_wr_core' generic HDL parameter. \
description = "Indicates whether we have a WR Core associated with this Fine Delay Core. Reflects the state of the <code>g_with_wr_core</code> generic HDL parameter. \
read 0: No WR Core present. Enabling WR will have no effect.\
read 1: WR Core available.";
type = BIT;
...
...
@@ -206,8 +204,10 @@ peripheral {
field {
name = "WR Core Time Ready";
prefix = "WR_READY";
description = "read 0: WR Core is not synchronied yet: there is no link, no PTP master in the network or synchronization is in progress.\
read 1: WR Core time is ready. User may enable WR reference by setting TCR.WR_ENABLE bit.";
description = "Indicates the status of synchronization of the associated WR core. Valid only if <code>TCR.WR_PRESENT</code> bit is set.\
read 0: WR Core is not synchronzied yet: there is no link, no PTP master in the network or synchronization is in progress.\
read 1: WR Core time is ready. User may enable WR reference by setting <code>TCR.WR_ENABLE</code> bit.\
<b>Note:</b> it is allowed to enable the WR mode even if <code>TCR.WR_READY</code> or <code>TCR.WR_LINK</code> bits are not set. Time base will be synced to WR as soon as the core gets correct PTP time from the master.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
...
...
@@ -216,7 +216,8 @@ peripheral {
field {
name = "WR Core Link Up";
prefix = "WR_LINK";
description = "read 0: Ethernet link is down.\
description = "Reflects the state of the WR Core's Ethernet link. Provided as an additional diagnostic feature.\
read 0: Ethernet link is down.\
read 1: Ethernet link is up.";
type = BIT;
access_bus = READ_ONLY;
...
...
@@ -226,8 +227,8 @@ peripheral {
field {
name = "Capture Current Time";
prefix = "CAP_TIME";
description = "Controls the readout of <code>TM_xxx</code> registers.\
write 1: transfers the current value of seconds/cycles counters to <code>TM_xxx</code> registers.\
description = "Performs an atomic read of the core's current time.\
write 1: transfers the current value of seconds/cycles counters to <code>TM_</code> registers.\
write 0: no effect.";
type = MONOSTABLE;
clock = "clk_ref_i";
...
...
@@ -236,11 +237,11 @@ peripheral {
field {
name = "Set Current Time";
prefix = "SET_TIME";
description = "Controls transfer of <code>TM_x</code> registers to the internal time counter.\
write 1: transfers the current value of <code>TM_x</code> to the timebase counters.\
description = "Sets internal time base counter to a given time in an atomic way:\
write 1: transfers the current value of <code>TM_</code> registers to the timebase counter.\
write 0: no effect.\
<b>Note:</b> Setting time also resynchronizes internal timebase counters, therefore \
time registers must be set after every reset/power cycle. ";
<b>Note 1:</b> Internal time counters must be always initialized to a known value (e.g. zeroes), after every reset/power cycle.\
<b>Note 2:</b> Writing to <code>TCR.SET_TIME</code> while WR mode is active is forbidden. If you do so, prepare for unforeseen consequences.";
type = MONOSTABLE;
clock = "clk_ref_i";
};
...
...
@@ -250,8 +251,9 @@ peripheral {
reg {
name = "Time Register - TAI seconds (MSB)";
prefix = "TM_SECH";
description = "read: value of internal seconds counter taken during write to <code>TCR.CAP_TIME</code> bit.\
write: new value of time (acked by writing <code>TCR.SET_TIME</code> bit)";
description = "Seconds counter, most significant part\
read: value of internal seconds counter taken upon last write to <code>TCR.CAP_TIME</code> bit.\
write: new value of seconds counter (loaded to the time base counter by writing <code>TCR.SET_TIME</code> bit)";
field {
name = "TAI seconds (MSB)";
size = 8;
...
...
@@ -266,8 +268,9 @@ peripheral {
reg {
name = "Time Register - TAI seconds (LSB)";
prefix = "TM_SECL";
description = "read: value of internal seconds counter taken during write to <code>TCR.CAP_TIME</code> bit.\
write: new value of time (acked by writing <code>TCR.SET_TIME</code> bit)";
description = "Seconds counter, least significant part\
read: value of internal seconds counter taken upon last write to <code>TCR.CAP_TIME</code> bit.\
write: new value of seconds counter (loaded to the time base counter by writing <code>TCR.SET_TIME</code> bit)";
description = "read: value of internal 125 MHz cycles counter taken during write to <code>TCR.CAP_TIME</code> bit.\
write: new value of time (acked by writing <code>TCR.SET_TIME</code> bit)";
description = "Number of 125 MHz reference clock cycles from the beginning of the current second. \
read: value of cycles counter taken upon last write to <code>TCR.CAP_TIME</code> bit.\
write: new value of cycles counter (loaded to the time base counter by writing <code>TCR.SET_TIME</code> bit)";
field {
name = "Reference clock cycles (0...124999999)";
size = 28;
...
...
@@ -296,8 +302,8 @@ peripheral {
};
reg {
name = "Host-driven TDC Data Register";
description = "28-bit data value read from / to be written to the ACAM. Used when bypass (host-driven) mode is active.";
name = "Host-driven TDC Data Register.";
description = "Holds the 28-bit data word read from/to be written to the ACAM TDC, when the core is configured in bypass mode (<code>GCR.BYPASS == 1</code>).";
prefix = "TDR";
field {
...
...
@@ -319,7 +325,8 @@ peripheral {
field {
name = "Write to TDC";
description = "write 1: write the data word programmed in <code>TDR</code> TDR register to the TDC. The TDC address must be set via the SPI I/O expander.\
description = "Writes the data word from <code>TDR</code> register to the ACAM TDC.\
write 1: write the data word programmed in <code>TDR</code> register to the TDC. The TDC address must be set via the SPI I/O expander.\
write 0: no effect.";
prefix = "WRITE";
clock = "clk_ref_i";
...
...
@@ -328,7 +335,8 @@ peripheral {
field {
name = "Read from TDC";
description = "write 1: read a data word from the TDC. The read word will be put in the <code>TDR</code> register. The TDC address must be set via the SPI I/O expander.\
description = "Reads a data word from the TDC and puts it in <code>TDR</code> register.\
write 1: read a data word from the TDC. The read word will be put in <code>TDR</code> register. The TDC address must be set via the SPI I/O expander.\
write 0: no effect.";
prefix = "READ";
clock = "clk_ref_i";
...
...
@@ -338,7 +346,9 @@ peripheral {
field {
clock = "clk_ref_i";
name = "Empty flag";
description = "Raw status of the EMPTY pin of the TDC. When zero, the internal TDC FIFO is empty (no timestamps to read)";
description = "Raw status of the <code>EF</code> (FIFO empty) pin of the TDC.\
read 0: there is one (or more) pending timestamp(s) in the ACAM's internal FIFO.\
read 1: the internal TDC FIFO is empty (no timestamps to read).";
prefix = "EMPTY";
type = BIT;
access_bus = READ_ONLY;
...
...
@@ -349,7 +359,7 @@ peripheral {
clock = "clk_ref_i";
name = "Stop enable";
description = "Controls the <code>StopDis</code> input of the TDC.\
write 1: disables the TDC stop input.\
write 1: enables the TDC stop input.\
write 0: no effect.";
prefix = "STOP_EN";
type = MONOSTABLE;
...
...
@@ -379,7 +389,7 @@ peripheral {
clock = "clk_ref_i";
name = "Stop disable";
description = "Controls the <code>StopDis</code> input of the TDC.\
write 1: enables the TDC stop input.\
write 1: disables the TDC stop input.\
write 0: no effect.";
prefix = "STOP_DIS";
type = MONOSTABLE;
...
...
@@ -389,7 +399,7 @@ peripheral {
clock = "clk_ref_i";
name = "Pulse <code>Alutrigger</code> line";
description = "Controls the TDC's <code>Alutrigger</code> line.\ Depending on the TDC's configuration, it can be used as a reset/FIFO clear/trigger signal.\
write 1: generates a pulse the <code>Alutrigger</code> line\
write 1: generates a pulse ACAM's <code>Alutrigger</code> line\
name = "Generate calibration pulses (type 1 calibration)";
description = "write 1: Generates a single calibration pulse on the TDC start input and the channels selected in the PSEL field.\
write 0: no effect.";
description = "Triggers generation of a calibration pulse on selected channels. Used to determine the exact 4/8ns setting tap of the fine delay line.\
write 1: immediately generates a single calibration pulse on the TDC start input and the output channels selected in the PSEL field.\
write 0: no effect.\
<b>Note:</b> In order for the pulse to be tagged by the TDC, it must be driven in the BYPASS mode and properly configured (I-mode, see driver/test program).";
description = "Drives the TDC stop input with a PPS signal synchronous to the FD core's timebase:\
write 1: feeds TDC input with internally generated PPS signal.\
write 0: PPS generation disabled.\
<b>Note:</b> Input multiplexer must be configured to drive the TDC trigger from the FPGA calibration output instead of the trigger input.";
prefix = "CAL_PPS";
type = BIT;
access_dev = READ_ONLY;
...
...
@@ -423,8 +437,10 @@ peripheral {
field {
name = "Produce DDMTD calibration pattern (type 2 calibration)";
description = "write 1: Enables DMTD test pattern generation on Delay chain input and output selected in PSEL.\
write 0: DMTD pattern generation disabled.";
description = "Controls DDMTD test pattern generation:\
write 1: enables DMTD test pattern on the TDC input and DDMTD sampling clock for the calibration flip-flops.\
write 0: DMTD pattern generation disabled.\
<b>Note:</b> Input multiplexer must be configured to drive the TDC trigger from the FPGA calibration output instead of the trigger input.";
prefix = "CAL_DMTD";
type = BIT;
access_dev = READ_ONLY;
...
...
@@ -434,8 +450,8 @@ peripheral {
field {
clock = "clk_ref_i";
name = "Calibration pulse output select/mask";
description = "1: enable generation of calibration pulses on the output corresponding to the written bit\
0: disable generation on the corresponding output";
description = "1: enable generation of type 1 calibration pulses (<code>CALR.CAL_PULSE</code>) on the output corresponding to the written bit\
0: disable pulse generation for the corresponding output ";
prefix = "PSEL";
type = SLV;
size = 4;
...
...
@@ -448,10 +464,13 @@ peripheral {
prefix = "DMTR_IN";
name = "DMTD Input Tag Register";
description = "Provides the DDMTD tag value for the input channel (type 2 calibration).";
field {
ack_read = "dmtr_in_rd_ack_o";
name = "DMTD Tag";
description = "The tag value.";
prefix = "TAG";
size = 31;
type = SLV;
...
...
@@ -461,6 +480,10 @@ peripheral {
field {
name = "DMTD Tag Ready";
description = "Tag ready flag (clear-on-read):\
1: a new DDMTD tag is available.\
0: tag not ready yet.";
prefix = "RDY";
type = BIT;
access_bus = READ_ONLY;
...
...
@@ -472,10 +495,13 @@ peripheral {
prefix = "DMTR_OUT";
name = "DMTD Output Tag Register";
description = "Provides the DDMTD tag value for a selected output channel (type 2 calibration).";
field {
ack_read = "dmtr_out_rd_ack_o";
name = "DMTD Tag";
description = "The tag value.";
prefix = "TAG";
size = 31;
type = SLV;
...
...
@@ -485,6 +511,11 @@ peripheral {
field {
name = "DMTD Tag Ready";
description = "Tag ready flag (clear-on-read):\
1: a new DDMTD tag is available.\
0: tag not ready yet.";
prefix = "RDY";
type = BIT;
access_bus = READ_ONLY;
...
...
@@ -494,11 +525,12 @@ peripheral {
reg {
prefix = "ADSFR";
name = "Acam to Delay line fractional part Scale Factor Register";
description = "Coefficient used to re-scale the fine part of the timestamp produced by Acam. Contains the number of Delay line bins per one Acam bin. Its value can be calculated with the following formula: <code>ADFSR = 2097.2 * ACAM bin size [ps]</code>";
name = "Acam Scaling Factor Register";
description = "Scaling factor between the FD's internal time scale and the ACAM's format. Used only in normal operating mode (<code>GCR.BYPASS == 0</code>).\
Formula (for G-Mode): <code>ADSFR = round(2097.152 * ACAM_bin_size [ps])</code>";
field {
name = "ADFSR Value";
name = "ADSFR Value";
size = 18;
type = SLV;
clock = "clk_ref_i";
...
...
@@ -510,10 +542,10 @@ peripheral {
reg {
prefix = "ATMCR";
name = "Acam Timestamp Merging Control Register";
description = "Register controlling the merging of the fine timestamps prouced by Acam with the coarse timestamps gatheret by the FPGA. These values are hardware-specific. The register should be loaded with the paramete 'ATMCR' from the mezzanine's configuration EEPROM";
description = "Controls merging of fine timestamps prouced by Acam with coarse timestamps obtained by the FPGA. See developers' manual for explanation. ";
field {
name = "Wraparound Coarse Threshold";
name = "Coarse threshold";
prefix = "C_THR";
size = 8;
type = SLV;
...
...
@@ -523,7 +555,7 @@ peripheral {
};
field {
name = "Wraparound Fine Threshold";
name = "Fine threshold";
prefix = "F_THR";
size = 23;
type = SLV;
...
...
@@ -536,7 +568,7 @@ peripheral {
reg {
prefix = "ASOR";
name = "Acam Start Offset Register";
description = "";
description = "ACAM timestamp start offset. Value that gets subtracted from ACAM's timestamps (due to ACAM's ALU architecture that does not support negative numbers). See developers' manual for explanation.";
description = "Write 1: resets the delay/pulse count counters (IECRAW, IECTAG and IEPD_WDELAY)\
description = "Write 1: resets the delay/pulse count counters (<code>IECRAW</code>, <code>IECTAG</code> and <code>IEPD.PDELAY</code>)\
write 0: no effect";
type = MONOSTABLE;
clock = "clk_ref_i";
...
...
@@ -595,7 +630,7 @@ peripheral {
field {
name = "Processing delay";
description = "Worst-case delay between the input event and the generation of its timestamp. Expressed as a number of 125 MHz clock cycles.";
description = "Worst-case delay between an input event and its timestamp being available. Expressed as a number of 125 MHz clock cycles.";
prefix = "PDELAY";
type = SLV;
size = 8;
...
...
@@ -608,7 +643,8 @@ peripheral {
reg {
name = "SPI Control Register";
prefix = "SCR";
description = "Single control register for the SPI Controller, allowing for single-cycle (non-waiting) updates of the DAC, GPIO & PLL.";
description = "Single control register for the SPI Controller, allowing for atomic updates of the DAC, GPIO and PLL.";
field {
name = "Data";
prefix = "DATA";
...
...
@@ -624,7 +660,8 @@ peripheral {
name = "Select DAC";
prefix = "SEL_DAC";
type = BIT;
description = "write 1: selects the DAC as the target peripheral of the transfer";
description = "write 1: selects the DAC as the target peripheral of the transfer\
write 0: no effect";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
...
...
@@ -632,7 +669,8 @@ peripheral {
name = "Select PLL";
prefix = "SEL_PLL";
type = BIT;
description = "write 1: selects the AD9516 PLL as the target peripheral of the transfer";
description = "write 1: selects the AD9516 PLL as the target peripheral of the transfer\
write 0: no effect";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
...
...
@@ -640,7 +678,8 @@ peripheral {
name = "Select GPIO";
prefix = "SEL_GPIO";
type = BIT;
description = "write 1: selects the MCP23S17 GPIO as the target peripheral of the transfer";
description = "write 1: selects the MCP23S17 GPIO as the target peripheral of the transfer\
write 0: no effect";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
...
...
@@ -650,15 +689,15 @@ peripheral {
prefix = "READY";
type = BIT;
description = "read 0: SPI controller is busy performing a transfer\
read 1: SPI controller has finished its previous transfer. Read-back data is available in the DATA field";
read 1: SPI controller has finished its previous transfer. Read-back data is available in <code>SCR.DATA</code>";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Clock Polarity";
description = "0: SPI clock is not inverted\
1: SPI clock is inverted";
description = "0: SPI clock is not inverted (data valid on rising edge)\
1: SPI clock is inverted (data valid on falling edge)";
prefix = "CPOL";
type = BIT;
access_bus = READ_WRITE;
...
...
@@ -669,7 +708,7 @@ peripheral {
name = "Transfer Start";
prefix = "START";
type = MONOSTABLE;
description = "write 1: Starts transfer to the selected peripheral\
description = "write 1: starts SPI transfer from/to the selected peripheral\
write 0: no effect";
};
};
...
...
@@ -678,11 +717,12 @@ peripheral {
reg {
name = "Reference Clock Rate Register";
prefix = "RCRR";
description = "Provides the momentary value of the internal clock rate counter. Can be used in conjunction with the DAC to roughly syntonize the card's reference clock with a clock coming from an external master installed in the same host (e.g. a CTRV/CTRP) in a software-only way.";
description = "Provides the momentary value of the internal clock rate counter. Can be used in conjunction with the DAC to roughly syntonize the card's reference clock with a clock coming from an external master installed in the same host (e.g. a CTRV/CTRP) in a software-only way or to measure tuning range of the local VCXO.";
field {
name = "Rate";
name = "Frequency";
description = "Reference clock frequency, in Hz";
type = SLV;
size = 32;
clock = "clk_ref_i";
...
...
@@ -695,13 +735,14 @@ peripheral {
reg {
name = "Timestamp Buffer Control Register";
prefix = "TSBCR";
description = "Controls timestamp readout from the core's circular buffer";
field {
name = "Channel Mask";
name = "Channel mask";
prefix = "CHAN_MASK";
description = "Selects which channels' time tags shall be written to the buffer. \
1: timestamp buffer is enabled. Readout is possible.\
0: timestamp buffer is disabled. Timestamps are processed (if set in delay mode), but discarded for readout.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
...
...
@@ -720,12 +764,16 @@ peripheral {
field {
name = "Buffer purge";
description = "write 1: clear timestamp buffer.\
write 0: no effect";
prefix = "PURGE";
type = MONOSTABLE;
};
field {
name = "Reset TS Sequence Numbers";
name = "Reset timestamp sequence number";
description = "write 1: reset timestamp sequence number counter\
write 0: no effect";
prefix = "RST_SEQ";
clock = "clk_ref_i";
type = MONOSTABLE;
...
...
@@ -734,6 +782,7 @@ peripheral {
field {
name = "Buffer full";
prefix = "FULL";
description = "read 1: buffer is full. Oldest timestamps (at the end of the buffer) are discarded as the new ones are coming.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
...
...
@@ -742,6 +791,8 @@ peripheral {
field {
name = "Buffer empty";
prefix = "EMPTY";
description = "read 1: buffer is empty.\
read 0: there is some data in the buffer.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
...
...
@@ -751,6 +802,7 @@ peripheral {
field {
name = "Buffer entries count";
prefix = "COUNT";
description = "Number of timestamps currently stored in the readout buffer";
type = SLV;
size = 12;
access_bus = READ_ONLY;
...
...
@@ -760,6 +812,9 @@ peripheral {
field {
name = "RAW readout mode enable";
prefix = "RAW";
description = "Enables raw timestamp readout mode (i.e. bypassing postprocessing). Used only for debugging purposes.\
write 1: enable raw mode\
write 0: disable raw mode (normal operation)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
...
...
@@ -770,9 +825,11 @@ peripheral {
name = "Timestamp Buffer Interrupt Register";
prefix = "TSBIR";
description = "Controls the behaviour of the core's readout interrupt (coalescing).";
field {
name = "IRQ timeout [milliseconds]";
description = "The IRQ line will be asserted after TIMEOUT milliseconds even if the amount of data in the buffer is below the THRESHOLD.";
description = "The IRQ line will be asserted after <code>TSBIR.TIMEOUT</code> milliseconds even if the amount of data in the buffer is below <code>TSBIR.THRESHOLD</code>.";
prefix = "TIMEOUT";
type = SLV;
size = 10;
...
...
@@ -782,7 +839,7 @@ peripheral {
field {
name = "Interrupt threshold";
description = "Number of samples (timestamps) in the buffer, which will immediately trigger an interrupt.";
description = "Minimum number of samples (timestamps) in the buffer that immediately triggers an interrupt.";
prefix = "THRESHOLD";
type = SLV;
size = 12;
...
...
@@ -823,7 +880,7 @@ peripheral {
prefix = "TSBR_CYCLES";
field {
name = "Cycles Value [in 8 ns ticks]";
name = "Timestamps cycles count (in 8 ns ticks)";
size = 28;
type = SLV;
access_bus = READ_ONLY;
...
...
@@ -832,14 +889,15 @@ peripheral {
};
reg {
name = "Timestamp Buffer Readout Fine / Channel / Seq ID Register";
name = "Timestamp Buffer Readout Fine/Channel/Sequence ID Register";
prefix = "TSBR_FID";
field {
name = "Channel ID";
prefix = "CHANNEL";
description = "ID of the originating channel):\
0 = TDC input, 1..4 = delay outputs";
description = "ID of the originating channel:\
<code>0</code>: TDC input\
<code>1..4</code>: outputs 1..4";
size = 4;
type = SLV;
access_bus = READ_ONLY;
...
...
@@ -847,7 +905,7 @@ peripheral {
};
field {
name = "Fine Value [in phase units]";
name = "Fine Value (in phase units)";
prefix = "FINE";
size = 12;
type = SLV;
...
...
@@ -868,11 +926,16 @@ peripheral {
};
reg {
name = "I2C bitbanged IO register";
name = "I2C Bit-banged IO Register";
description = "Controls state of the mezzanine's I2C bus lines by means of bitbanging";
prefix = "I2CR";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
description = "write 0: drive SCL to 0 \
write 1: drive SCL to weak 1 (pullup)";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
...
...
@@ -881,21 +944,29 @@ peripheral {
field {
name = "SDA Line out";
prefix = "SDA_OUT";
description = "write 0: drive SDA to 0 \
write 1: drive SDA to weak 1 (pullup)";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
description = "State of the SCL line.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
description = "State of the SDA line.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
...
...
@@ -904,11 +975,12 @@ peripheral {
reg {
name = "Test/Debug register 1";
name = "Test/Debug Register 1";
prefix = "TDER1";
field {
name = "VCXO Frequency";
description = "Mezzanine VCXO frequency in Hz, measured using the system clock as a reference. Used during factory test only.";
prefix = "VCXO_FREQ";
size = 32;
type = SLV;
...
...
@@ -918,11 +990,12 @@ peripheral {
};
reg {
name = "Test/Debug register 1";
name = "Test/Debug Register 1";
prefix = "TDER2";
field {
name = "Peltier PWM drive";
description = "Peltier module PWM drive. Lab-only feature for measuring temperature characteristics of the board.";
prefix = "PELT_DRIVE";
size = 32;
type = SLV;
...
...
@@ -937,6 +1010,7 @@ peripheral {
field {
name = "Debug value";
description = "Additional register for holding timestamp debug data (used only in raw readout mode). Content format is not specified.";
size = 32;
type = SLV;
access_bus = READ_ONLY;
...
...
@@ -950,7 +1024,7 @@ peripheral {
field {
name = "Advance buffer readout";
descriptor = "write 1: transfer the latest sample from the ring buffer to TSBR_SEC/CYCLES/FID registers,\
descriptor = "write 1: transfer the latest sample from the ring buffer to <code>TSBR_SECH</code>, <code>TSBR_SECL</code>, <code>TSBR_CYCLES</code> and <code>TSBR_FID</code> registers,\
write 0: no effect";
type = MONOSTABLE;
prefix = "ADV";
...
...
@@ -959,19 +1033,22 @@ peripheral {
irq {
name = "TS Buffer not empty.";
name = "Timestamp Buffer interrupt.";
description = "Triggers when there are timestamps in the readout buffer";
trigger = LEVEL_1;
prefix = "ts_buf_notempty";
};
irq {
name = "DMTD Softpll interrupt";
name = "DMTD SoftPLL interrupt";
description = "Unused in current design";
trigger = EDGE_RISING;
prefix = "dmtd_spll";
};
irq {
name = "Sync Status Changed";
description = "Triggers when the synchronization source status has changed (usually: loss/acquisition of WR clock)";