Commit 4e9db31d authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

rtl,doc: fixes in Wishbone registers documentation

parent 14302385
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......@@ -838,7 +838,7 @@ The main register block controls all subsystems of the FD core excluding the One
@section Output stage registers
@node{Output stage registers}
The output stage register blocks control independently, the 4 outputs of the FD Core.
The output stage register block controls a single FD output stage.
@include fd_channel_regs.in
......@@ -866,6 +866,10 @@ The output stage register blocks control independently, the 4 outputs of the FD
@item ACAM TDC-GPX datasheet
@url{http://www.acam.de/fileadmin/Download/pdf/English/DB_GPX_e.pdf‎}
@item Sockit 1-Wire master project page
@url{http://opencores.org/project,sockit_owm}
@end itemize
@bye
......@@ -15,6 +15,8 @@
`define FD_DCR_FORCE_DLY 32'h00000040
`define FD_DCR_NO_FINE_OFFSET 7
`define FD_DCR_NO_FINE 32'h00000080
`define FD_DCR_FORCE_HI_OFFSET 8
`define FD_DCR_FORCE_HI 32'h00000100
`define ADDR_FD_FRR 6'h4
`define ADDR_FD_U_STARTH 6'h8
`define ADDR_FD_U_STARTL 6'hc
......
......@@ -75,9 +75,9 @@
`define ADDR_FD_ADSFR 8'h30
`define ADDR_FD_ATMCR 8'h34
`define FD_ATMCR_C_THR_OFFSET 0
`define FD_ATMCR_C_THR 32'h0000000f
`define FD_ATMCR_F_THR_OFFSET 4
`define FD_ATMCR_F_THR 32'h07fffff0
`define FD_ATMCR_C_THR 32'h000000ff
`define FD_ATMCR_F_THR_OFFSET 8
`define FD_ATMCR_F_THR 32'h7fffff00
`define ADDR_FD_ASOR 8'h38
`define FD_ASOR_OFFSET_OFFSET 0
`define FD_ASOR_OFFSET 32'h007fffff
......
#!/bin/bash
wbgen2 -V fd_main_wishbone_slave.vhd -H record -p fd_main_wbgen2_pkg.vhd -K ../include/regs/fd_main_regs.vh -s defines -C fd_main_regs.h -D doc/fd_main_regs.html fd_main_wishbone_slave.wb
wbgen2 -V fd_channel_wishbone_slave.vhd -H record -p fd_channel_wbgen2_pkg.vhd -K ../include/regs/fd_channel_regs.vh -s defines -C fd_channel_regs.h -D doc/fd_channel_regs.html fd_channel_wishbone_slave.wb
\ No newline at end of file
wbgen2 -V fd_main_wishbone_slave.vhd -H record -p fd_main_wbgen2_pkg.vhd -K ../include/regs/fd_main_regs.vh -s defines -C fd_main_regs.h -f texinfo -D ../../doc/design-notes/fd_main_regs.in fd_main_wishbone_slave.wb
wbgen2 -V fd_channel_wishbone_slave.vhd -H record -p fd_channel_wbgen2_pkg.vhd -K ../include/regs/fd_channel_regs.vh -s defines -C fd_channel_regs.h -f texinfo -D ../../doc/design-notes/fd_channel_regs.in fd_channel_wishbone_slave.wb
\ No newline at end of file
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......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Fri Feb 15 12:07:17 2013
-- Created : Thu Jul 4 10:40:48 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Fri Feb 15 12:07:17 2013
-- Created : Thu Jul 4 10:40:48 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -533,7 +533,7 @@ begin
end process;
-- Start Delay Update
-- Update delay/absolute trigger time
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -550,8 +550,8 @@ begin
end process;
-- Delay Update Done
-- synchronizer chain for field : Delay Update Done (type RO/WO, clk_ref_i -> clk_sys_i)
-- Delay update done flag
-- synchronizer chain for field : Delay update done flag (type RO/WO, clk_ref_i -> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -564,7 +564,7 @@ begin
end process;
-- Force Calibration Delay
-- Force calibration delay
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -581,11 +581,11 @@ begin
end process;
-- Disable Fine Part update
-- Disable fine part update
regs_o.dcr_no_fine_o <= fd_channel_dcr_no_fine_int;
-- Force Output High
-- Force output high
regs_o.dcr_force_hi_o <= fd_channel_dcr_force_hi_int;
-- Fine Range
-- Fine range in SY89825 taps.
regs_o.frr_o <= fd_channel_frr_int;
-- TAI seconds (MSB)
regs_o.u_starth_o <= fd_channel_u_starth_int;
......
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......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Fri Feb 15 12:07:16 2013
-- Created : Thu Jul 4 10:40:48 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Fri Feb 15 12:07:16 2013
-- Created : Thu Jul 4 10:40:48 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -1330,17 +1330,17 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- State of the reset Line of the FMC Card
-- pass-through field: State of the reset Line of the FMC Card in register: Reset Register
-- State of the reset Line of the Mezzanine (EXT_RST_N pin)
-- pass-through field: State of the reset Line of the Mezzanine (EXT_RST_N pin) in register: Reset Register
regs_o.rstr_rst_fmc_o <= wrdata_reg(0);
-- State of the reset of the Fine Delay HDL Core
-- pass-through field: State of the reset of the Fine Delay HDL Core in register: Reset Register
-- State of the reset of the Fine Delay Core
-- pass-through field: State of the reset of the Fine Delay Core in register: Reset Register
regs_o.rstr_rst_core_o <= wrdata_reg(1);
-- Reset magic value
-- pass-through field: Reset magic value in register: Reset Register
regs_o.rstr_lock_o <= wrdata_reg(31 downto 16);
-- Bypass Hardware TDC/Delay Controller
-- synchronizer chain for field : Bypass Hardware TDC/Delay Controller (type RW/RO, clk_sys_i <-> clk_ref_i)
-- Bypass hardware TDC controller
-- synchronizer chain for field : Bypass hardware TDC controller (type RW/RO, clk_sys_i <-> clk_ref_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1371,8 +1371,8 @@ begin
end process;
-- PLL Locked
-- Mezzanine Present
-- PLL lock status
-- Mezzanine present
-- DMTD Clock Status
-- WR Timing Enable
regs_o.tcr_wr_enable_o <= fd_main_tcr_wr_enable_int;
......@@ -1684,8 +1684,8 @@ begin
end process;
-- PPS Calibration output enable
-- synchronizer chain for field : PPS Calibration output enable (type RW/RO, clk_sys_i <-> clk_ref_i)
-- PPS calibration output enable.
-- synchronizer chain for field : PPS calibration output enable. (type RW/RO, clk_sys_i <-> clk_ref_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1726,8 +1726,8 @@ begin
-- DMTD Tag Ready
-- DMTD Tag
-- DMTD Tag Ready
-- ADFSR Value
-- asynchronous std_logic_vector register : ADFSR Value (type RW/RO, clk_ref_i <-> clk_sys_i)
-- ADSFR Value
-- asynchronous std_logic_vector register : ADSFR Value (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1746,8 +1746,8 @@ begin
end process;
-- Wraparound Coarse Threshold
-- asynchronous std_logic_vector register : Wraparound Coarse Threshold (type RW/RO, clk_ref_i <-> clk_sys_i)
-- Coarse threshold
-- asynchronous std_logic_vector register : Coarse threshold (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1766,8 +1766,8 @@ begin
end process;
-- Wraparound Fine Threshold
-- asynchronous std_logic_vector register : Wraparound Fine Threshold (type RW/RO, clk_ref_i <-> clk_sys_i)
-- Fine threshold
-- asynchronous std_logic_vector register : Fine threshold (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1806,8 +1806,8 @@ begin
end process;
-- Number of raw events
-- asynchronous std_logic_vector register : Number of raw events (type RO/WO, clk_ref_i <-> clk_sys_i)
-- Number of raw events.
-- asynchronous std_logic_vector register : Number of raw events. (type RO/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1907,8 +1907,8 @@ begin
end process;
-- Rate
-- asynchronous std_logic_vector register : Rate (type RO/WO, clk_ref_i <-> clk_sys_i)
-- Frequency
-- asynchronous std_logic_vector register : Frequency (type RO/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1927,8 +1927,8 @@ begin
end process;
-- Channel Mask
-- asynchronous std_logic_vector register : Channel Mask (type RW/RO, clk_ref_i <-> clk_sys_i)
-- Channel mask
-- asynchronous std_logic_vector register : Channel mask (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1962,7 +1962,7 @@ begin
end process;
-- Reset TS Sequence Numbers
-- Reset timestamp sequence number
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1990,9 +1990,9 @@ begin
regs_o.tsbir_threshold_o <= fd_main_tsbir_threshold_int;
-- Timestamps TAI Seconds (bits 39-32)
-- Timestamps TAI Seconds (bits 31-0)
-- Cycles Value [in 8 ns ticks]
-- Timestamps cycles count (in 8 ns ticks)
-- Channel ID
-- Fine Value [in phase units]
-- Fine Value (in phase units)
-- Timestamp Sequence ID
-- SCL Line out
regs_o.i2cr_scl_out_o <= fd_main_i2cr_scl_out_int;
......
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