Commit 3bb91660 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

rtl/fine_delay_core: updated component connections

parent 238a3c24
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2012-04-25 -- Last update: 2012-05-21
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -253,6 +253,7 @@ architecture rtl of fine_delay_core is ...@@ -253,6 +253,7 @@ architecture rtl of fine_delay_core is
signal tag_frac : std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0); signal tag_frac : std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
signal tag_coarse : std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0); signal tag_coarse : std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
signal tag_utc : std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0); signal tag_utc : std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal tag_dbg : std_logic_vector(31 downto 0);
signal tag_valid : std_logic; signal tag_valid : std_logic;
signal rbuf_mux_ts : t_timestamp_array(0 to 4); signal rbuf_mux_ts : t_timestamp_array(0 to 4);
...@@ -271,7 +272,7 @@ architecture rtl of fine_delay_core is ...@@ -271,7 +272,7 @@ architecture rtl of fine_delay_core is
signal rst_n_sys, rst_n_ref : std_logic; signal rst_n_sys, rst_n_ref : std_logic;
signal advance_rbuf : std_logic; signal tsbcr_read_ack, fid_read_ack : std_logic;
signal irq_rbuf, irq_spll, irq_sync : std_logic; signal irq_rbuf, irq_spll, irq_sync : std_logic;
...@@ -463,7 +464,8 @@ begin -- rtl ...@@ -463,7 +464,8 @@ begin -- rtl
irq_ts_buf_notempty_i => irq_rbuf, irq_ts_buf_notempty_i => irq_rbuf,
irq_dmtd_spll_i => irq_spll, irq_dmtd_spll_i => irq_spll,
irq_sync_status_i => irq_sync, irq_sync_status_i => irq_sync,
advance_rbuf_o => advance_rbuf, tsbcr_read_ack_o => tsbcr_read_ack,
fid_read_ack_o => fid_read_ack,
spllr_rd_ack_o => spllr_rd_ack, spllr_rd_ack_o => spllr_rd_ack,
calr_rd_ack_o => calr_rd_ack calr_rd_ack_o => calr_rd_ack
); );
...@@ -496,6 +498,7 @@ begin -- rtl ...@@ -496,6 +498,7 @@ begin -- rtl
tag_coarse_o => tag_coarse, tag_coarse_o => tag_coarse,
tag_utc_o => tag_utc, tag_utc_o => tag_utc,
tag_valid_o => tag_valid, tag_valid_o => tag_valid,
tag_dbg_raw_o => tag_dbg,
tag_rearm_p1_i => '1', tag_rearm_p1_i => '1',
...@@ -549,8 +552,10 @@ begin -- rtl ...@@ -549,8 +552,10 @@ begin -- rtl
tag_utc_i => rbuf_in_ts.u, tag_utc_i => rbuf_in_ts.u,
tag_coarse_i => rbuf_in_ts.c, tag_coarse_i => rbuf_in_ts.c,
tag_frac_i => rbuf_in_ts.f, tag_frac_i => rbuf_in_ts.f,
tag_dbg_raw_i => tag_dbg,
advance_rbuf_i => advance_rbuf, tsbcr_read_ack_i => tsbcr_read_ack,
fid_read_ack_i => fid_read_ack,
buf_irq_o => irq_rbuf, buf_irq_o => irq_rbuf,
regs_i => regs_fromwb, regs_i => regs_fromwb,
regs_o => regs_towb_rbuf); regs_o => regs_towb_rbuf);
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2012-04-25 -- Last update: 2012-05-21
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -53,24 +53,24 @@ package fine_delay_pkg is ...@@ -53,24 +53,24 @@ package fine_delay_pkg is
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Timestamp field bits (if you change them, you must also change the WB files) -- Timestamp field bits (if you change them, you must also change the WB files)
constant c_TIMESTAMP_UTC_BITS : integer := 40; constant c_TIMESTAMP_UTC_BITS : integer := 40;
constant c_TIMESTAMP_COARSE_BITS : integer := 28; constant c_TIMESTAMP_COARSE_BITS : integer := 28;
constant c_TIMESTAMP_FRAC_BITS : integer := 12; constant c_TIMESTAMP_FRAC_BITS : integer := 12;
-- log2(Number of entries in the timestamp buffer) -- log2(Number of entries in the timestamp buffer)
constant c_RING_BUFFER_SIZE_LOG2 : integer := 10; constant c_RING_BUFFER_SIZE_LOG2 : integer := 10;
-- Reference clock frequency in Hz -- Reference clock frequency in Hz
constant c_REF_CLK_FREQ : integer := 125000000; constant c_REF_CLK_FREQ : integer := 125000000;
-- System clock frequency in Hz -- System clock frequency in Hz
constant c_SYS_CLK_FREQ : integer := 62500000; constant c_SYS_CLK_FREQ : integer := 62500000;
-- Reference clock period in picoseconds -- Reference clock period in picoseconds
constant c_REF_CLK_PERIOD_PS : integer := 8000; constant c_REF_CLK_PERIOD_PS : integer := 8000;
-- Number of card outputs -- Number of card outputs
constant c_FD_NUM_OUTPUTS : integer := 4; constant c_FD_NUM_OUTPUTS : integer := 4;
-- Number of reference clock cycles per one DDMTD calibration period -- Number of reference clock cycles per one DDMTD calibration period
constant c_FD_DMTD_CALIBRATION_PERIOD : integer := 125; constant c_FD_DMTD_CALIBRATION_PERIOD : integer := 125;
...@@ -93,7 +93,7 @@ package fine_delay_pkg is ...@@ -93,7 +93,7 @@ package fine_delay_pkg is
dev_version => x"00000001", dev_version => x"00000001",
dev_date => x"20120425", dev_date => x"20120425",
description => "Fine Delay Core "); description => "Fine Delay Core ");
type t_fd_timestamp is record type t_fd_timestamp is record
u : std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0); u : std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
c : std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0); c : std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
...@@ -183,6 +183,7 @@ package fine_delay_pkg is ...@@ -183,6 +183,7 @@ package fine_delay_pkg is
tag_coarse_o : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0); tag_coarse_o : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
tag_utc_o : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0); tag_utc_o : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_rearm_p1_i : in std_logic; tag_rearm_p1_i : in std_logic;
tag_dbg_raw_o : out std_logic_vector(31 downto 0);
tag_valid_o : out std_logic; tag_valid_o : out std_logic;
csync_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0); csync_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
csync_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0); csync_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
...@@ -214,7 +215,7 @@ package fine_delay_pkg is ...@@ -214,7 +215,7 @@ package fine_delay_pkg is
regs_i : in t_fd_main_out_registers; regs_i : in t_fd_main_out_registers;
regs_o : out t_fd_main_in_registers; regs_o : out t_fd_main_in_registers;
tcr_rd_ack_i : in std_logic; tcr_rd_ack_i : in std_logic;
csync_pps_o: out std_logic; csync_pps_o : out std_logic;
irq_sync_o : out std_logic); irq_sync_o : out std_logic);
end component; end component;
...@@ -254,7 +255,8 @@ package fine_delay_pkg is ...@@ -254,7 +255,8 @@ package fine_delay_pkg is
tcr_rd_ack_o : out std_logic; tcr_rd_ack_o : out std_logic;
calr_rd_ack_o : out std_logic; calr_rd_ack_o : out std_logic;
spllr_rd_ack_o : out std_logic; spllr_rd_ack_o : out std_logic;
advance_rbuf_o : out std_logic; tsbcr_read_ack_o : out std_logic;
fid_read_ack_o: out std_logic;
irq_ts_buf_notempty_i : in std_logic; irq_ts_buf_notempty_i : in std_logic;
irq_dmtd_spll_i : in std_logic; irq_dmtd_spll_i : in std_logic;
irq_sync_status_i : in std_logic; irq_sync_status_i : in std_logic;
...@@ -329,24 +331,25 @@ package fine_delay_pkg is ...@@ -329,24 +331,25 @@ package fine_delay_pkg is
dmtd_dac_wr_o : out std_logic); dmtd_dac_wr_o : out std_logic);
end component; end component;
component fd_ring_buffer component fd_ring_buffer
generic ( generic (
g_size_log2 : integer); g_size_log2 : integer);
port ( port (
rst_n_sys_i : in std_logic; rst_n_sys_i : in std_logic;
rst_n_ref_i : in std_logic; rst_n_ref_i : in std_logic;
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
tag_valid_i : in std_logic; tag_valid_i : in std_logic;
tag_source_i : in std_logic_vector(3 downto 0); tag_source_i : in std_logic_vector(3 downto 0);
tag_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0); tag_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0); tag_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
tag_frac_i : in std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0); tag_frac_i : in std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
advance_rbuf_i : in std_logic; tag_dbg_raw_i : in std_logic_vector(31 downto 0);
buf_irq_o : out std_logic; tsbcr_read_ack_i : in std_logic;
regs_i : in t_fd_main_out_registers; fid_read_ack_i : in std_logic;
regs_o : out t_fd_main_in_registers); buf_irq_o : out std_logic;
regs_i : in t_fd_main_out_registers;
regs_o : out t_fd_main_in_registers);
end component; end component;
component fd_spi_dac_arbiter component fd_spi_dac_arbiter
...@@ -376,7 +379,7 @@ package fine_delay_pkg is ...@@ -376,7 +379,7 @@ package fine_delay_pkg is
q_o : out std_logic); q_o : out std_logic);
end component; end component;
component fine_delay_core component fine_delay_core
generic ( generic (
g_with_wr_core : boolean; g_with_wr_core : boolean;
g_simulation : boolean; g_simulation : boolean;
......
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