description = "Writing 0xDEADBEEF into this register will trigger a full reset of the \ fine delay core";
description = "Writing 0xDEADBEEF into this register will trigger a full reset of the \ fine delay core";
type = PASS_THROUGH;
type = PASS_THROUGH;
size = 32;
size = 32;
};
};
};
};
reg {
reg {
name = "ID Register";
name = "ID Register";
...
@@ -33,32 +34,32 @@ peripheral {
...
@@ -33,32 +34,32 @@ peripheral {
};
};
reg {
reg {
name = "Global Control Register";
name = "Global Control Register";
prefix = "GCR";
prefix = "GCR";
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "Bypass delay block";
name = "Bypass delay block";
prefix = "BYPASS";
prefix = "BYPASS";
description = "0: normal operation (fine-delay)\
description = "0: normal operation (fine-delay)\
1: TDC and delay lines controlled from the host";
1: TDC and delay lines controlled from the host";
type = BIT;
type = BIT;
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "Enable trigger input";
name = "Enable trigger input";
prefix = "INPUT_EN";
prefix = "INPUT_EN";
description = "";
description = "";
type = BIT;
type = BIT;
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
field {
field {
name = "Internal Counter Sync";
name = "Internal Counter Sync";
...
@@ -85,123 +86,154 @@ peripheral {
...
@@ -85,123 +86,154 @@ peripheral {
prefix = "WR_READY";
prefix = "WR_READY";
type = BIT;
type = BIT;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
};
};
reg {
reg {
name = "TDC Address/Data Register";
name = "TDC Address/Data Register";
prefix = "TAR";
prefix = "TAR";
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "DATA";
name = "DATA";
prefix = "DATA";
prefix = "DATA";
type = SLV;
type = SLV;
size = 28;
size = 28;
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
load = LOAD_EXT;
};
};
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "ADDR";
name = "ADDR";
prefix = "ADDR";
prefix = "ADDR";
type = SLV;
type = SLV;
size = 4;
size = 4;
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
reg {
reg {
name = "TDC control/status reg";
name = "TDC control/status reg";
prefix = "TDCSR";
prefix = "TDCSR";
field {
field {
name = "Start TDC write";
name = "Start TDC write";
prefix = "WRITE";
prefix = "WRITE";
clock = "clk_ref_i";
clock = "clk_ref_i";
type = MONOSTABLE;
type = MONOSTABLE;
};
};
field {
field {
name = "Start TDC read";
name = "Start TDC read";
prefix = "READ";
prefix = "READ";
clock = "clk_ref_i";
clock = "clk_ref_i";
type = MONOSTABLE;
type = MONOSTABLE;
};
};
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "Error flag";
name = "Error flag";
prefix = "ERR";
prefix = "ERR";
type = BIT;
type = BIT;
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "Interrupt flag";
name = "Interrupt flag";
prefix = "INT";
prefix = "INT";
type = BIT;
type = BIT;
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "Load flag";
name = "Load flag";
prefix = "LOAD";
prefix = "LOAD";
type = BIT;
type = BIT;
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "Empty flag";
name = "Empty flag";
prefix = "EMPTY";
prefix = "EMPTY";
type = BIT;
type = BIT;
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "Start enable";
name = "Start disable";
prefix = "STOP_EN";
prefix = "START_DIS";
type = MONOSTABLE;
type = MONOSTABLE;
};
};
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "Start disable";
name = "Start enable";
prefix = "START_DIS";
prefix = "START_EN";
type = MONOSTABLE;
type = MONOSTABLE;
};
};
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "Stop enable";
name = "Start disable";
prefix = "START_EN";
prefix = "STOP_DIS";
type = MONOSTABLE;
type = MONOSTABLE;
};
};
field {
field {
clock = "clk_ref_i";
clock = "clk_ref_i";
name = "Stop disable";
name = "Start enable";
prefix = "STOP_DIS";
prefix = "STOP_EN";
type = MONOSTABLE;
type = MONOSTABLE;
};
};
field {
};
clock = "clk_ref_i";
name = "write 1: Pulse the Alutrigger line";
prefix = "ALUTRIG";
type = MONOSTABLE;
};
};
reg {
prefix = "CALR";
name = "Calibration register";
field {
clock = "clk_ref_i";
name = "Triggers calibration pulses";
description = "write 1: Generates synchronous calibration pulses the channels selected in PSEL field.";
prefix = "CAL_PULSE";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "Enable pulse generation";
description = "1: enable generation of calibration pulses on the output corresponding to the written bit\
0: disable generation of these pulses";
prefix = "PSEL";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
reg {
...
@@ -216,85 +248,85 @@ peripheral {
...
@@ -216,85 +248,85 @@ peripheral {
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
reg {
reg {
prefix = "ATMCR";
prefix = "ATMCR";
name = "Acam Timestamp Merging Control Register";
name = "Acam Timestamp Merging Control Register";
description = "Register controlling the merging of the fine timestamps prouced by Acam with the coarse timestamps gatheret by the FPGA. These values are hardware-specific. The register should be loaded with the paramete 'ATMCR' from the mezzanine's configuration EEPROM";
description = "Register controlling the merging of the fine timestamps prouced by Acam with the coarse timestamps gatheret by the FPGA. These values are hardware-specific. The register should be loaded with the paramete 'ATMCR' from the mezzanine's configuration EEPROM";
field {
field {
name = "Wraparound Coarse Threshold";
name = "Wraparound Coarse Threshold";
prefix = "C_THR";
prefix = "C_THR";
size = 4;
size = 4;
type = SLV;
type = SLV;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
field {
field {
name = "Wraparound Fine Threshold";
name = "Wraparound Fine Threshold";
prefix = "F_THR";
prefix = "F_THR";
size = 23;
size = 23;
type = SLV;
type = SLV;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
reg {
reg {
prefix = "ASOR";
prefix = "ASOR";
name = "Acam Start Offset Register";
name = "Acam Start Offset Register";
description = "";
description = "";
field {
field {
name = "Start Offset";
name = "Start Offset";
prefix = "OFFSET";
prefix = "OFFSET";
size = 23;
size = 23;
type = SLV;
type = SLV;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
reg {
reg {
name = "Raw Input Events Counter Register ";
name = "Raw Input Events Counter Register ";
prefix = "IECRAW";
prefix = "IECRAW";
field {
field {
name = "Number of raw events";
name = "Number of raw events";
description = "Number of all input pulses detected by the timestamper";
description = "Number of all input pulses detected by the timestamper";
type = SLV;
type = SLV;
size = 32;
size = 32;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev= WRITE_ONLY;
access_dev= WRITE_ONLY;
};
};
};
};
reg {
reg {
name = "Tagged Input Events Counter Register ";
name = "Tagged Input Events Counter Register ";
prefix = "IECTAG";
prefix = "IECTAG";
field {
field {
name = "Number of tagged events";
name = "Number of tagged events";
description = "Number of all input pulses which passed the width checks and have produced valid timestamps.";
description = "Number of all input pulses which passed the width checks and have produced valid timestamps.";
type = SLV;
type = SLV;
size = 32;
size = 32;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev= WRITE_ONLY;
access_dev= WRITE_ONLY;
};
};
};
};
reg {
reg {
name = "Input Event Processing Delay Register";
name = "Input Event Processing Delay Register";
prefix = "IEPD";
prefix = "IEPD";
field {
field {
name = "Reset stats";
name = "Reset stats";
...
@@ -302,20 +334,20 @@ peripheral {
...
@@ -302,20 +334,20 @@ peripheral {
description = "Write 1: resets the delay/pulse count counters (IECRAW, IECTAG and IEPD_WDELAY)\
description = "Write 1: resets the delay/pulse count counters (IECRAW, IECTAG and IEPD_WDELAY)\
write 0: no effect";
write 0: no effect";
type = MONOSTABLE;
type = MONOSTABLE;
clock = "clk_ref_i";
clock = "clk_ref_i";
};
};
field {
field {
name = "Processing delay";
name = "Processing delay";
description = "Worst-case delay between the input event and the generation of its timestamp. Expressed as a number of 125 MHz clock cycles.";
description = "Worst-case delay between the input event and the generation of its timestamp. Expressed as a number of 125 MHz clock cycles.";
prefix = "PDELAY";
prefix = "PDELAY";
type = SLV;
type = SLV;
size = 8;
size = 8;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
};
};
-- reg {
-- reg {
-- name = "SPI Control Register";
-- name = "SPI Control Register";
...
@@ -332,7 +364,7 @@ peripheral {
...
@@ -332,7 +364,7 @@ peripheral {
-- access_dev = READ_WRITE;
-- access_dev = READ_WRITE;
-- access_bus = READ_WRITE;
-- access_bus = READ_WRITE;
-- };
-- };
-- field {
-- field {
-- name = "Select DAC";
-- name = "Select DAC";
-- prefix = "SEL_DAC";
-- prefix = "SEL_DAC";
...
@@ -405,7 +437,7 @@ peripheral {
...
@@ -405,7 +437,7 @@ peripheral {
};
};
reg {
reg {
name = "Reference Clock Frequency Register";
name = "Reference Clock Frequency Register";
prefix = "RCFR";
prefix = "RCFR";
description = "Current frequency of the reference clock. Used for testing/calibration purposes.";
description = "Current frequency of the reference clock. Used for testing/calibration purposes.";
...
@@ -420,55 +452,55 @@ peripheral {
...
@@ -420,55 +452,55 @@ peripheral {
}
}
};
};
reg {
reg {
name = "Timestamp Buffer Control Register";
name = "Timestamp Buffer Control Register";
prefix = "TSBCR";
prefix = "TSBCR";
field {
field {
name = "Buffer enable";
name = "Buffer enable";
prefix = "ENABLE";
prefix = "ENABLE";
type = BIT;
type = BIT;
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
field {
field {
name = "Buffer purge";
name = "Buffer purge";
prefix = "PURGE";
prefix = "PURGE";
type = MONOSTABLE;
type = MONOSTABLE;
};
};
field {
field {
name = "Reset TS Sequence Number";
name = "Reset TS Sequence Number";
prefix = "RST_SEQ";
prefix = "RST_SEQ";
clock = "clk_ref_i";
clock = "clk_ref_i";
type = MONOSTABLE;
type = MONOSTABLE;
};
};
field {
field {
name = "Buffer full";
name = "Buffer full";
prefix = "FULL";
prefix = "FULL";
type = BIT;
type = BIT;
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
field {
field {
name = "Buffer empty";
name = "Buffer empty";
prefix = "EMPTY";
prefix = "EMPTY";
type = BIT;
type = BIT;
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
};
};
irq {
irq {
name = "TS Buffer not empty";
name = "TS Buffer not empty";
trigger = LEVEL_0;
trigger = LEVEL_0;
prefix = "ts_buf_notempty";
prefix = "ts_buf_notempty";
};
};
reg {
reg {
name = "Timestamp Buffer Readout UTC Register";
name = "Timestamp Buffer Readout UTC Register";
...
@@ -479,7 +511,7 @@ peripheral {
...
@@ -479,7 +511,7 @@ peripheral {
size = 32;
size = 32;
type = SLV;
type = SLV;
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
};
};
...
@@ -492,60 +524,60 @@ peripheral {
...
@@ -492,60 +524,60 @@ peripheral {
size = 28;
size = 28;
type = SLV;
type = SLV;
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
};
};
reg {
reg {
name = "Timestamp Buffer Readout Fine / Seq ID Register";
name = "Timestamp Buffer Readout Fine / Seq ID Register";
prefix = "TSBR_FID";
prefix = "TSBR_FID";
field {
field {
name = "Fine Value [in phase units]";
name = "Fine Value [in phase units]";
prefix = "FINE";
prefix = "FINE";
size = 12;
size = 12;
type = SLV;
type = SLV;
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
field {
field {
name = "Timestamp Sequence ID";
name = "Timestamp Sequence ID";
prefix = "SEQID";
prefix = "SEQID";
align = 16;
align = 16;
size = 16;
size = 16;
type = SLV;
type = SLV;
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
ack_read = "advance_rbuf_o";
ack_read = "advance_rbuf_o";
};
};
};
};
fifo_reg {
fifo_reg {
direction = CORE_TO_BUS;
direction = CORE_TO_BUS;
size = 256;
size = 256;
prefix = "RAWFIFO";
prefix = "RAWFIFO";
name = "RAW FIFO";
name = "RAW FIFO";
flags_bus = {FIFO_EMPTY};
flags_bus = {FIFO_EMPTY};
flags_dev = {FIFO_FULL};
flags_dev = {FIFO_FULL};
clock = "clk_ref_i";
clock = "clk_ref_i";
field {
field {
name = "RawFrac";
name = "RawFrac";
prefix = "FRAC";
prefix = "FRAC";
size = 28;
size = 28;
type = SLV;
type = SLV;
};
};
field {
field {
name = "RawCoarse";
name = "RawCoarse";
prefix = "COARSE";
prefix = "COARSE";
size = 28;
size = 28;
type = SLV;
type = SLV;
};
};
};
};
};
};
channel_template = {
channel_template = {
...
@@ -587,176 +619,176 @@ channel_template = {
...
@@ -587,176 +619,176 @@ channel_template = {
Note that the time written to [U/C/F]START must be bigger by at least 200 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much bigger, as it's affected by the non-determinism of the operating system.";
Note that the time written to [U/C/F]START must be bigger by at least 200 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much bigger, as it's affected by the non-determinism of the operating system.";
type = BIT;
type = BIT;
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
load = LOAD_EXT;
clock = "clk_ref_i";
clock = "clk_ref_i";
};
};
field {
field {
name = "Pulse generator triggered";
name = "Pulse generator triggered";
prefix = "PG_TRIG";
prefix = "PG_TRIG";
description = "read 1: pulse generator has been triggered and produced a pulse\
description = "read 1: pulse generator has been triggered and produced a pulse\
read 0: pulse generator is busy or hasn't triggered yet";
read 0: pulse generator is busy or hasn't triggered yet";
type = BIT;
type = BIT;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
field {
field {
name = "Start Delay Update";
name = "Start Delay Update";
prefix = "UPDATE";
prefix = "UPDATE";
description = "write 1: Starts delay update procedure. The start and end times from [U/C/F][START/END] will be transferred in an atomic way to the internal delay/pulse generator registers\
description = "write 1: Starts delay update procedure. The start and end times from [U/C/F][START/END] will be transferred in an atomic way to the internal delay/pulse generator registers\
write 0: no effect.";
write 0: no effect.";
type = MONOSTABLE;
type = MONOSTABLE;
clock = "clk_ref_i";
clock = "clk_ref_i";
};
};
field {
field {
name = "Delay Update Done";
name = "Delay Update Done";
prefix = "UPD_DONE";
prefix = "UPD_DONE";
description = "read 1: The delays from [U/C/F][START/END] have been loaded into internal registers\
description = "read 1: The delays from [U/C/F][START/END] have been loaded into internal registers\
read 0: update operation in progress";
read 0: update operation in progress";
clock = "clk_ref_i";
clock = "clk_ref_i";
type = BIT;
type = BIT;
access_bus = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
field {
field {
name = "Force Calibration Pulse";
name = "Force Calibration Delay";
prefix = "FORCE_CP";
prefix = "FORCE_DLY";
description = "write 1: preloads the delay line with the contents of FRR register and produces a single-cycle (8ns) pulse at the beginning of the ACAM Start period. Used for self-calibration purposes\
description = "write 1: preloads the delay line with the contents of FRR register. Used for self-calibration purposes.\
write 0: no effect";
write 0: no effect";
clock = "clk_ref_i";
clock = "clk_ref_i";
type = MONOSTABLE;
type = MONOSTABLE;
};
};
field {
field {
name = "Output Polarity";
name = "Output Polarity";
prefix = "POL";
prefix = "POL";
description = "1: output is active HIGH\
description = "1: output is active HIGH\
0: output is active LOW";
0: output is active LOW";
clock = "clk_ref_i";
clock = "clk_ref_i";
type = BIT;
type = BIT;
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
reg {
reg {
name = "Fine Range Register (channel %d)";
name = "Fine Range Register (channel %d)";
prefix = "FRR%d";
prefix = "FRR%d";
description = "Delay line tap setting at which the line generates an 8 ns (one cycle) longer delay than when set to 0.";
description = "Delay line tap setting at which the line generates an 8 ns (one cycle) longer delay than when set to 0.";
field {
field {
name = "Fine Range";
name = "Fine Range";
size = 10;
size = 10;
type = SLV;
type = SLV;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
reg {
reg {
name = "Pulse start time / offset (UTC part, channel %d)";
name = "Pulse start time / offset (UTC part, channel %d)";
prefix = "U_START%d";
prefix = "U_START%d";
description = "UTC part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).";
description = "UTC part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).";
field {
field {
name = "UTC seconds";
name = "UTC seconds";
size = 32;
size = 32;
type = SLV;
type = SLV;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
reg {
reg {
name = "Pulse start time / offset (8 ns cycles, channel %d)";
name = "Pulse start time / offset (8 ns cycles, channel %d)";
prefix = "C_START%d";
prefix = "C_START%d";
description = "Sub-second part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
description = "Sub-second part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
field {
field {
name = "Refclk cycles";
name = "Refclk cycles";
size = 28;
size = 28;
type = SLV;
type = SLV;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
reg {
reg {
name = "Pulse start time / offset (sub-cycle fine part, channel %d)";
name = "Pulse start time / offset (sub-cycle fine part, channel %d)";
prefix = "F_START%d";
prefix = "F_START%d";
description = "Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
description = "Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
field {
field {
name = "Fractional part";
name = "Fractional part";
size = 12;
size = 12;
type = SLV;
type = SLV;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
reg {
reg {
name = "Pulse end time / offset (UTC part, channel %d)";
name = "Pulse end time / offset (UTC part, channel %d)";
prefix = "U_END%d";
prefix = "U_END%d";
description = "UTC part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode).";
description = "UTC part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode).";
field {
field {
name = "UTC seconds";
name = "UTC seconds";
size = 32;
size = 32;
type = SLV;
type = SLV;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
reg {
reg {
name = "Pulse end time / offset (8 ns cycles, channel %d)";
name = "Pulse end time / offset (8 ns cycles, channel %d)";
prefix = "C_END%d";
prefix = "C_END%d";
description = "Sub-second part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
description = "Sub-second part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
field {
field {
name = "Refclk cycles";
name = "Refclk cycles";
size = 28;
size = 28;
type = SLV;
type = SLV;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
reg {
reg {
name = "Pulse end time / offset (sub-cycle fine part, channel %d)";
name = "Pulse end time / offset (sub-cycle fine part, channel %d)";
prefix = "F_END%d";
prefix = "F_END%d";
description = "Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
description = "Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
field {
field {
name = "Fractional part";
name = "Fractional part";
size = 12;
size = 12;
type = SLV;
type = SLV;
clock = "clk_ref_i";
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
};
};
};
};
...
@@ -769,10 +801,10 @@ function generate_channels(n)
...
@@ -769,10 +801,10 @@ function generate_channels(n)
