hdl/rtl/fd_acam_timestamper: reset FIFO after each sample

26a05382 · Tomasz Wlostowski · 8c28309f · 26a05382 · 26a05382
Commit 26a05382 authored Feb 23, 2013 by Tomasz Wlostowski
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Showing with 60 additions and 84 deletions

fd_acam_timestamp_postprocessor.vhd hdl/rtl/fd_acam_timestamp_postprocessor.vhd +3 -5

fd_acam_timestamper.vhd hdl/rtl/fd_acam_timestamper.vhd +57 -79

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--- a/hdl/rtl/fd_acam_timestamp_postprocessor.vhd
+++ b/hdl/rtl/fd_acam_timestamp_postprocessor.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-29
-- Last update: 2012-05-18
+-- Last update: 2013-02-21
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -60,12 +60,10 @@ entity fd_acam_timestamp_postprocessor is

    raw_valid_i : in std_logic;
    raw_utc_i   : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
-    raw_utc_shifted_i   : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);

    -- "start number" (value of coarse counter, counting at every start pulse of the
    -- TDC, i.e. 125 MHz / 16 = 7.8215 MHz)
    raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
-    raw_coarse_shifted_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);

    -- raw fractional timestamp generated by ACAM
    raw_frac_i : in std_logic_vector(22 downto 0);
@@ -224,8 +222,8 @@ begin  -- behavioral
          tag_frac_o <= raw_frac_i(11 downto 0);
          tag_dbg_raw_o(10 downto 0) <= raw_frac_i(22 downto 12);
          tag_dbg_raw_o(15 downto 11) <= acam_subcycle_offset_i;
-          tag_dbg_raw_o(23 downto 16) <= raw_coarse_shifted_i(7 downto 0);
-          tag_dbg_raw_o(31 downto 24) <= raw_utc_shifted_i(7 downto 0);
+          tag_dbg_raw_o(23 downto 16) <= raw_coarse_i(7 downto 0);
+          tag_dbg_raw_o(31 downto 24) <= raw_utc_i(7 downto 0);

          tag_valid_o <= '1';
        else

--- a/hdl/rtl/fd_acam_timestamper.vhd
+++ b/hdl/rtl/fd_acam_timestamper.vhd