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# Heatsinks for the FMC Fine Delay
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This page summarizes the heatsink testing results.
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This page summarizes the heatsink testing results. All tests made with
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version EDA-02267-V6-0.
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## Fine Delay on SVEC (lab test)
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... | ... | @@ -229,8 +230,9 @@ needed. |
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## Thermal imaging
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tbc
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h2. Thermal camera measurements
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tbc
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## Thermal camera measurements
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## Replacing the LVPECL delay lines with LVDS counterparts
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... | ... | @@ -239,8 +241,17 @@ with an LVDS version: ICS854S296I-33. Temperature test |
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(identical conditions) performed on a SVEC showed 5 degrees less on the
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modified card:
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\- new delay line 51.31 Celsius
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\- old delay line 56.38 Celsius
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- new delay line (LVDS) 51.31 Celsius
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- old delay line (PECL) 56.38 Celsius
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Note that the EDA-02267-V6-0 PCB is not foreseen for the LVPECL
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termination resistors for the new delay line chip. In case we decide to
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use the new chip, for production purposes a new revision of the PCB
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should be made.
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-----
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15 August 2014
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