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# Preliminary specs
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- 1 ns resolution.
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- 10 us - 500 us range.
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- 1 input.
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- 1 ns resolution or better.
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- 10 us - 500 us range or better.
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- 1 input, selectable between front panel and FMC connector.
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- 8 individually controllable outputs.
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- Input and outputs are LVDS, all in a single LVDS connector. Level
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translation will be performed in a separate active patch panel.
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- Input and outputs are LVDS, all in a single parallel LVDS connector.
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Level translation will be performed in a separate active patch
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panel.
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- Delay circuit reacts on input rising edge. Minimum input pulse
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width: 100 ns.
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- Output pulse width is programmable in steps of system clock ticks
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