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side\_a\_s.JPG side\_b\_s.JPG
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# Functional system specifications
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## Functional system specifications
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- 1 ns resolution or better.
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- Accuracy: */- (500 ps* timebase accuracy).
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-----
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# Preliminary ideas for the technical specifications
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## Technical specification
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- Baseline solution: TDC at the inputs followed by coarse count in the
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FPGA and fine delay chips at the outputs. To be considered for
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-----
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# Schematics & PCB
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## Detailed project information
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PDF with schematics and PCB design is available here:
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http://svn.ohwr.org/fmc-delay-1ns-8cha/trunk/circuit_board/fmc-delay-1ns-8cha/Schematics/fmc-delay.pdf
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- [PDF with schematics and PCB
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design](http://svn.ohwr.org/fmc-delay-1ns-8cha/trunk/circuit_board/fmc-delay-1ns-8cha/Schematics/fmc-delay.pdf)
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- Card aka FMC6
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# Project Status
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-----
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## Project Status
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<table>
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<tbody>
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</tr>
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<tr class="odd">
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<td>03-02-2011</td>
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<td>Prototype PCB assembled and ready for HDL development</td>
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<td>Prototype PCB assembled and ready for HDL development. ID EEPROM works.</td>
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</tr>
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<tr class="even">
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<td>03-02-2011</td>
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<td>(1 hour later) Prototype powered up. No smoke observed. ID EEPROM works.</td>
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<td>14-02-2011</td>
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<td>Design being reviewed by CERN's design office.</td>
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</tr>
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<tr class="odd">
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<td>21-02-2011</td>
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<td>HDL development on-going.</td>
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</tr>
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</tbody>
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</table>
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-----
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Erik van der Bij - 28 January 2011
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Erik van der Bij - 21 February 2011
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