... | ... | @@ -10,6 +10,10 @@ |
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<td>22-04-2010</td>
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<td>Start working on project</td>
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</tr>
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<tr class="odd">
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<td>30-04-2010</td>
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<td>First meeting with N. Voumard to fine-tune functional specs</td>
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</tr>
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</tbody>
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</table>
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... | ... | @@ -20,13 +24,14 @@ |
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- 1 input, selectable between front panel and FMC connector. This
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input is shared by all output channels.
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- Input electrical standard will be TTL, with optional 50 Ohm
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termination.
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- Output standards to be supported: 50 Ohm TTL drivers (with 2V/ns or
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faster rising edges) and 50 Ohm blocking (0-15V) drivers.
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- 8 individually controllable outputs, with independent delay, width
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termination. A LED will signal termination status.
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- Output standard: 50 Ohm TTL drivers (with 2V/ns or faster rising
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edges).
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- 4 individually controllable outputs, with independent delay, width
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and enable/disable.
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- Delay circuit reacts on input rising or falling edge (programmable).
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Minimum input pulse width: 100 ns.
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- SMC connectors for inputs and outputs.
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- Delay circuit reacts on input rising edge. Minimum input pulse
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width: 100 ns.
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- Output pulse width is programmable in steps of system clock ticks
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(~125 MHz) with a 16-bit register per output channel.
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- Jitter will be measured by probing the positive pins of two output
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... | ... | @@ -38,9 +43,6 @@ |
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# Preliminary ideas for the technical specifications
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- The system could be split in two parts: an FMC with LVDS I/O and
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parallel connectors plus one or more patch panels for level
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conversion.
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- Baseline solution: TDC at the inputs followed by coarse count in the
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FPGA and fine delay chips at the outputs. To be considered for
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improving jitter: monolithic FFs in the FMC, before the fine delay
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... | ... | |