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</tbody>
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</table>
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# Preliminary specs
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# Preliminary functional system specifications
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- 1 ns resolution or better.
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- 1 us - 120 s range or better.
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- 1 input, selectable between front panel and FMC connector. This
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input is shared by all output channels.
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- Input electrical standard will be TTL, with optional 50 Ohm
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termination.
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- Output standards to be supported: 50 Ohm TTL drivers and 50 Ohm
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blocking (0-15V) drivers.
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- 8 individually controllable outputs, with independent delay, width
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and enable/disable.
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- Input and outputs are LVDS, all in a single parallel LVDS connector.
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Level translation will be performed in a separate active patch
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panel.
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- Delay circuit reacts on input rising or falling edge (programmable).
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Minimum input pulse width: 100 ns.
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- Output pulse width is programmable in steps of system clock ticks
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of the distribution of delay measurements between the rising edges
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of any two channels should not exceed 100 ps. This should hold for
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any programmed delay within the whole delay range.
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- Accuracy better than 200 ps for delays smaller than 1 ms.
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# Preliminary ideas for the technical specifications
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- The system could be split in two parts: an FMC with LVDS I/O and
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parallel connectors plus one or more patch panels for level
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conversion.
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- Baseline solution: TDC at the inputs followed by coarse count in the
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FPGA and fine delay chips at the outputs. To be considered for
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improving jitter: monolithic FFs in the FMC, before the fine delay
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chips.
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