... | ... | @@ -35,6 +35,8 @@ |
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(counter initialized by SW) giving ~ms accuracy. Later, with a
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WR-enabled solution, they can be much more accurate.
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-----
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# Preliminary ideas for the technical specifications
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- Baseline solution: TDC at the inputs followed by coarse count in the
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... | ... | @@ -43,6 +45,8 @@ |
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chips. Continuous calibration of fine delay chips might be needed to
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compensate for Process-Voltage-Temperature (PVT) effects.
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-----
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# Project Status
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<table>
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... | ... | @@ -53,16 +57,28 @@ |
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</tr>
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<tr class="even">
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<td>22-04-2010</td>
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<td>Start working on project</td>
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<td>Start working on project.</td>
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</tr>
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<tr class="odd">
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<td>30-04-2010</td>
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<td>First meeting with N. Voumard to fine-tune functional specs</td>
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<td>First meeting with N. Voumard to fine-tune functional specs.</td>
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</tr>
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<tr class="even">
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|
<td>20-05-2010</td>
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<td>Second functional specs meeting with the ABT team</td>
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<td>Second functional specs meeting with the ABT team.</td>
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</tr>
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<tr class="odd">
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<td>11-06-2010</td>
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<td>Order <a href="https://edh.cern.ch/Document/SupplyChain/DAI/4384595">4384595</a> made for design of the module.</td>
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</tr>
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<tr class="even">
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<td>15-06-2010</td>
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<td>Date reserved for Final functional specification review meeting.</td>
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</tr>
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</tbody>
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</table>
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-----
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Erik van der Bij - 11 June 2010
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