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# Preliminary specs
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- 1 ns resolution or better.
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- 10 us - 500 us range or better.
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- 1 input, selectable between front panel and FMC connector.
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- 8 individually controllable outputs.
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- 1 us - 120 s range or better.
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- 1 input, selectable between front panel and FMC connector. This
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input is shared by all output channels.
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- 8 individually controllable outputs, with independent delay, width
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and enable/disable.
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- Input and outputs are LVDS, all in a single parallel LVDS connector.
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Level translation will be performed in a separate active patch
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panel.
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- Delay circuit reacts on input rising edge. Minimum input pulse
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width: 100 ns.
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- Delay circuit reacts on input rising or falling edge (programmable).
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Minimum input pulse width: 100 ns.
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- Output pulse width is programmable in steps of system clock ticks
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(~125 MHz) with a 16-bit register per output channel.
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- Jitter will be measured by probing the positive pins of two output
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channels which have been programmed with the same delay. The sigma
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of the distribution of delay measurements between the rising edges
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of any two channels should not exceed 100 ps. This should hold for
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any programmed delay withing the nominal range.
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any programmed delay within the whole delay range.
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