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fmc dac 600m 12b 1cha dds - Testing
Commit ad6ecf9e authored by Marek Gumiński's avatar Marek Gumiński
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Updated PTS to FMC hardware version 3.

parent 99babf85
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.gitmodules
View file @ ad6ecf9e
[submodule "gateware/ip_cores/wr-cores"] [submodule "gateware/ip_cores/wr-cores"]
path = gateware/ip_cores/wr-cores path = gateware/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git url = https://ohwr.org/project/wr-cores.git
[submodule "gateware/ip_cores/general-cores"] [submodule "gateware/ip_cores/general-cores"]
path = gateware/ip_cores/general-cores path = gateware/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git url = https://ohwr.org/project/general-cores.git
[submodule "gateware/ip_cores/gn4124-core"] [submodule "gateware/ip_cores/gn4124-core"]
path = gateware/ip_cores/gn4124-core path = gateware/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git url = https://ohwr.org/project/gn4124-core.git
[submodule "software/wrpc-sw"] [submodule "software/wrpc-sw"]
path = software/wrpc-sw path = software/wrpc-sw
url = git://ohwr.org/hdl-core-lib/wr-cores/wrpc-sw.git url = https://ohwr.org/project/wrpc-sw.git
[submodule "gateware/ip_cores/etherbone-core"] [submodule "gateware/ip_cores/etherbone-core"]
path = gateware/ip_cores/etherbone-core path = gateware/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git url = https://ohwr.org/project/etherbone-core.git
[submodule "software/fpga-config-space"] [submodule "software/fpga-config-space"]
path = software/fpga-config-space path = software/fpga-config-space
url = git://ohwr.org/hdl-core-lib/fpga-config-space.git url = https://ohwr.org/project/fpga-config-space.git
[submodule "software/fmc-adc-100m14b4cha-sw/zio"] [submodule "software/fmc-adc-100m14b4cha-sw/zio"]
path = software/fmc-adc-100m14b4cha-sw/zio path = software/fmc-adc-100m14b4cha-sw/zio
url = git://ohwr.org/misc/zio.git url = https://ohwr.org/project/zio.git
doc/DAC-DDS_PTS_TestingProcedure.docx 100644 → 100755
View file @ ad6ecf9e
No preview for this file type
doc/DAC-DDS_PTS_UserGuide.docx 100644 → 100755
View file @ ad6ecf9e
No preview for this file type
doc/ad9510_pts_ad9510_beam.stp 0 → 100644
View file @ ad6ecf9e
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"00","00010000","10"
"02","00100000","20"
"04","00000000","00"
"05","00000000","00"
"06","00011001","19"
"07","00000000","00"
"08","00000100","04"
"09","00000000","00"
"0A","00000101","05"
"0B","00000000","00"
"0C","00000000","00"
"0D","00000000","00"
"34","00000001","01"
"35","00000000","00"
"36","00000000","00"
"37","00000100","04"
"38","00000001","01"
"39","00000000","00"
"3A","00000000","00"
"3B","00000100","04"
"3C","00001000","08"
"3D","00001010","0A"
"3E","00001010","0A"
"3F","00001000","08"
"40","00000011","03"
"41","00000011","03"
"42","00000010","02"
"43","00000011","03"
"44","00010011","13"
"45","00011101","1D"
"48","00100010","22"
"49","10000000","80"
"4A","00000000","00"
"4B","00000000","00"
"4C","00010001","11"
"4D","00000000","00"
"4E","01010101","55"
"4F","10000000","80"
"50","00000000","00"
"51","00000000","00"
"52","00010001","11"
"53","00000000","00"
"54","00010001","11"
"55","00000000","00"
"56","00000000","00"
"57","00000000","00"
"58","00000000","00"
"59","00000000","00"
"5A","00000000","00"
""
"Other Settings..."
"RefIn:",10
"CLKInp1:",500
"CLKInp2:",500
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
doc/ad9510_pts_ad9510_ref.stp 0 → 100644
View file @ ad6ecf9e
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"00","00010000","10"
"02","00100000","20"
"04","00000000","00"
"05","00000000","00"
"06","00011001","19"
"07","00000000","00"
"08","00000100","04"
"09","00000000","00"
"0A","00000101","05"
"0B","00000000","00"
"0C","00000000","00"
"0D","00000000","00"
"34","00000001","01"
"35","00000000","00"
"36","00000000","00"
"37","00000100","04"
"38","00000001","01"
"39","00000000","00"
"3A","00000000","00"
"3B","00000100","04"
"3C","00001000","08"
"3D","00001010","0A"
"3E","00001010","0A"
"3F","00001000","08"
"40","00000011","03"
"41","00000011","03"
"42","00000010","02"
"43","00000011","03"
"44","00010011","13"
"45","00011101","1D"
"48","00100010","22"
"49","10000000","80"
"4A","00000000","00"
"4B","00000000","00"
"4C","00010001","11"
"4D","00000000","00"
"4E","01010101","55"
"4F","10000000","80"
"50","00000000","00"
"51","00000000","00"
"52","00010001","11"
"53","00000000","00"
"54","00010001","11"
"55","10000000","80"
"56","00000000","00"
"57","00000000","00"
"58","00000000","00"
"59","00000000","00"
"5A","00000000","00"
""
"Other Settings..."
"RefIn:",10
"CLKInp1:",125
"CLKInp2:",500
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
doc/ad9510_pts_dds_slave.stp 0 → 100644
View file @ ad6ecf9e
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00010000","10"
"0002","00100000","20"
"0004","00000000","00"
"0005","00000000","00"
"0006","00011001","19"
"0007","00000000","00"
"0008","00000100","04"
"0009","00000000","00"
"000A","00000100","04"
"000B","00000000","00"
"000C","00000000","00"
"000D","00000000","00"
"0034","00000001","01"
"0035","00000000","00"
"0036","00000000","00"
"0037","00000100","04"
"0038","00000001","01"
"0039","00000000","00"
"003A","00000000","00"
"003B","00000100","04"
"003C","00001000","08"
"003D","00001000","08"
"003E","00001000","08"
"003F","00001000","08"
"0040","00000010","02"
"0041","00000010","02"
"0042","00000010","02"
"0043","00000011","03"
"0044","00010011","13"
"0045","00000000","00"
"0048","00100010","22"
"0049","10000000","80"
"004A","00000000","00"
"004B","00000000","00"
"004C","00010001","11"
"004D","00000000","00"
"004E","01010101","55"
"004F","00000000","00"
"0050","00000000","00"
"0051","00000000","00"
"0052","00010001","11"
"0053","00000000","00"
"0054","01000100","44"
"0055","00000000","00"
"0056","00000000","00"
"0057","00000000","00"
"0058","00000000","00"
"0059","00000000","00"
"005A","00000000","00"
""
"Other Settings..."
"RefIn:",10
"CLKInp1:",500
"CLKInp2:",500
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
doc/ad9510_pts_delayline_new.stp 0 → 100644
View file @ ad6ecf9e
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"00","00010000","10"
"02","00100000","20"
"04","00000000","00"
"05","00000000","00"
"06","00011001","19"
"07","00000000","00"
"08","00000100","04"
"09","00000000","00"
"0A","00000001","01"
"0B","00000000","00"
"0C","00000000","00"
"0D","00000000","00"
"34","00000001","01"
"35","00000000","00"
"36","00000000","00"
"37","00000100","04"
"38","00000001","01"
"39","00000000","00"
"3A","00000000","00"
"3B","00000100","04"
"3C","00001000","08"
"3D","00001000","08"
"3E","00001000","08"
"3F","00001000","08"
"40","00000010","02"
"41","00000010","02"
"42","00000010","02"
"43","00000011","03"
"44","00010011","13"
"45","00000000","00"
"48","00100010","22"
"49","10000000","80"
"4A","00000000","00"
"4B","00000000","00"
"4C","00010001","11"
"4D","00000000","00"
"4E","01010101","55"
"4F","00000000","00"
"50","00000000","00"
"51","00000000","00"
"52","00010001","11"
"53","00000000","00"
"54","00010001","11"
"55","00000000","00"
"56","00000000","00"
"57","00000000","00"
"58","00000000","00"
"59","00000000","00"
"5A","00000000","00"
""
"Other Settings..."
"RefIn:",10
"CLKInp1:",1200
"CLKInp2:",500
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
doc/ad9510_pts_test.stp 0 → 100644
View file @ ad6ecf9e
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00010000","10"
"0002","00100000","20"
"0004","00000000","00"
"0005","00000000","00"
"0006","00011001","19"
"0007","00000100","04"
"0008","01000111","47"
"0009","00110000","30"
"000A","00000110","06"
"000B","00000000","00"
"000C","00000001","01"
"000D","00100000","20"
"0034","00000001","01"
"0035","00000000","00"
"0036","00000000","00"
"0037","00000100","04"
"0038","00000001","01"
"0039","00000000","00"
"003A","00000000","00"
"003B","00000100","04"
"003C","00001000","08"
"003D","00001011","0B"
"003E","00001011","0B"
"003F","00001000","08"
"0040","00000011","03"
"0041","00000011","03"
"0042","00000000","00"
"0043","00000011","03"
"0044","00010011","13"
"0045","00000000","00"
"0048","00000000","00"
"0049","00000000","00"
"004A","00000000","00"
"004B","00000000","00"
"004C","00010001","11"
"004D","00000000","00"
"004E","01000100","44"
"004F","00000000","00"
"0050","00000000","00"
"0051","00000000","00"
"0052","00010001","11"
"0053","00000000","00"
"0054","01000100","44"
"0055","00000000","00"
"0056","00000000","00"
"0057","00000000","00"
"0058","00000000","00"
"0059","00000000","00"
"005A","00000000","00"
""
"Other Settings..."
"RefIn:",10
"CLKInp1:",500
"CLKInp2:",500
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
doc/ad9516_pts_orig.stp 0 → 100644
View file @ ad6ecf9e
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","10011001","99"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000101","05"
"0012","00000000","00"
"0013","00001100","0C"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000000","00"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00100000","20"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001010","0A"
"0140","01000110","46"
"0141","01000110","46"
"0142","01000110","46"
"0143","01000110","46"
"0190","00000000","00"
"0191","10000000","80"
"0192","00000000","00"
"0193","10111011","BB"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","00000000","00"
"0198","00000000","00"
"0199","00010001","11"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00010001","11"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000001","01"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",25
"REF 2:",30.72
"VCO:",1500
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
doc/ad9516_pts_orig_cmos8.stp 0 → 100644
View file @ ad6ecf9e
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","10011001","99"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000101","05"
"0012","00000000","00"
"0013","00001100","0C"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000000","00"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00100000","20"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001010","0A"
"0140","01000110","46"
"0141","01000111","47"
"0142","01011110","5E"
"0143","01000111","47"
"0190","00000000","00"
"0191","10000000","80"
"0192","00000000","00"
"0193","10111011","BB"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","00000000","00"
"0198","00000000","00"
"0199","00010001","11"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00010001","11"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000001","01"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",25
"REF 2:",30.72
"VCO:",1500
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
doc/new_ad9516_pts_ad9510_clk.stp 0 → 100644
View file @ ad6ecf9e
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111101","7D"
"0011","00000001","01"
"0012","00000000","00"
"0013","00000110","06"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000100","04"
"0017","10110111","B7"
"0018","00000110","06"
"0019","00000000","00"
"001A","00000101","05"
"001B","00000000","00"
"001C","00000001","01"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001000","08"
"00F4","00001000","08"
"00F5","00001010","0A"
"0140","01000010","42"
"0141","01000011","43"
"0142","01000011","43"
"0143","01000011","43"
"0190","00000000","00"
"0191","10000000","80"
"0192","00000000","00"
"0193","01000100","44"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","10000000","80"
"0198","00000000","00"
"0199","01000100","44"
"019A","00000000","00"
"019B","00010001","11"
"019C","00110000","30"
"019D","00000000","00"
"019E","00100010","22"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00000000","00"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000001","01"
"01E1","00000001","01"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",10
"REF 2:",30.72
"VCO:",1500
"CLK:",10
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
doc/new_ad9516_pts_delayline.stp 0 → 100644
View file @ ad6ecf9e
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000001","01"
"0012","00000000","00"
"0013","00000110","06"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000100","04"
"0017","10110111","B7"
"0018","00000110","06"
"0019","00000000","00"
"001A","00000101","05"
"001B","00000000","00"
"001C","00000001","01"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001000","08"
"00F4","00001000","08"
"00F5","00001010","0A"
"0140","01000010","42"
"0141","01000011","43"
"0142","01000011","43"
"0143","01000011","43"
"0190","00000000","00"
"0191","10000000","80"
"0192","00000000","00"
"0193","01000100","44"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","10000000","80"
"0198","00000000","00"
"0199","00010001","11"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00100010","22"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00000000","00"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000001","01"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",10
"REF 2:",30.72
"VCO:",1500
"CLK:",10
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
doc/new_ad9516_pts_test.stp 0 → 100644
View file @ ad6ecf9e
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000001","01"
"0012","00000000","00"
"0013","00000110","06"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000100","04"
"0017","10110111","B7"
"0018","00000110","06"
"0019","00000000","00"
"001A","00000101","05"
"001B","00000000","00"
"001C","00000001","01"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001000","08"
"00F4","00001000","08"
"00F5","00001010","0A"
"0140","01000010","42"
"0141","01000011","43"
"0142","01000011","43"
"0143","01000011","43"
"0190","00000000","00"
"0191","10000000","80"
"0192","00000000","00"
"0193","01000100","44"
"0194","00000000","00"
"0195","00000000","00"
"0196","11111111","FF"
"0197","00000000","00"
"0198","00000000","00"
"0199","01000100","44"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00100010","22"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00000000","00"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000001","01"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",10
"REF 2:",30.72
"VCO:",1500
"CLK:",10
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
doc/pll_configuration_sw.txt 0 → 100644
View file @ ad6ecf9e
https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9516-1.html#eb-relatedsoftware
drivers_test.sh
View file @ ad6ecf9e
#!/bin/bash #!/bin/bash
rmmod fmc_adc_100m14b 2> /dev/null rmmod fmc_adc_100m14b 2> /dev/null
rmmod zio 2> /dev/null rmmod zio 2> /dev/null
rmmod rawrabbit 2> /dev/null rmmod rawrabbit 2> /dev/null
rmmod spec 2> /dev/null rmmod spec 2> /dev/null
rmmod fmc 2> /dev/null rmmod fmc 2> /dev/null
rmmod cp210x 2>/dev/null
rmmod usbtmc 2>/dev/null
prg=$0 prg=$0
if [ ! -e "$prg" ]; then if [ ! -e "$prg" ]; then
case $prg in case $prg in
...@@ -24,8 +19,7 @@ dir=$( ...@@ -24,8 +19,7 @@ dir=$(
) || exit ) || exit
prg=$dir/$(basename -- "$prg") || exit prg=$dir/$(basename -- "$prg") || exit
top=`echo "$prg" | sed 's/fmcdac600m12b1chadds.*/fmcdac600m12b1chadds\//'` top=`dirname -- "$prg"`
insmod "$top/software/fmc-bus/kernel/fmc.ko" insmod "$top/software/fmc-bus/kernel/fmc.ko"
...@@ -33,8 +27,8 @@ insmod "$top/software/spec-sw/kernel/spec.ko" "fw_name=../../$top/gateware/spec- ...@@ -33,8 +27,8 @@ insmod "$top/software/spec-sw/kernel/spec.ko" "fw_name=../../$top/gateware/spec-
insmod "$top/software/fmc-adc-100m14b4cha-sw/zio/zio.ko" insmod "$top/software/fmc-adc-100m14b4cha-sw/zio/zio.ko"
insmod "$top/software/fmc-adc-100m14b4cha-sw/kernel/fmc-adc-100m14b.ko" "gateware=../../$top/gateware/spec-fmc-adc-v4.0.bin" insmod "$top/software/fmc-adc-100m14b4cha-sw/kernel/fmc-adc-100m14b.ko" "gateware=../../$top/gateware/spec-fmc-adc-v4.0.bin"
adc=`python -c 'import sys; sys.path.append('\'python\''); import spec_identification; spec_identification.adc_bus()'` adc=`python -c "import sys; sys.path.append('$top/python'); import spec_identification; spec_identification.adc_bus()"`
dut=`python -c 'import sys; sys.path.append('\'python\''); import spec_identification; spec_identification.dut_bus()'` dut=`python -c "import sys; sys.path.append('$top/python'); import spec_identification; spec_identification.dut_bus()"`
echo "Please verify if both SPEC cards were correctly identified" echo "Please verify if both SPEC cards were correctly identified"
echo "" echo ""
echo "Files belowe are named with following pattern:" echo "Files belowe are named with following pattern:"
...@@ -46,7 +40,7 @@ echo "ls /sys/bus/fmc/devices/" ...@@ -46,7 +40,7 @@ echo "ls /sys/bus/fmc/devices/"
ls /sys/bus/fmc/devices/ ls /sys/bus/fmc/devices/
echo "" echo ""
if [ $adc -ge 0 ] if [ "$adc" -ge 0 ]
then then
echo "FmcAdc100m14b was found on bus $adc" echo "FmcAdc100m14b was found on bus $adc"
else else
...@@ -54,7 +48,7 @@ else ...@@ -54,7 +48,7 @@ else
echo "Make sure that single FmcAdc100m14b board is mounted in PCIe slot and that it contain valid eeprom content" echo "Make sure that single FmcAdc100m14b board is mounted in PCIe slot and that it contain valid eeprom content"
fi fi
if [ $dut -ge 0 ] if [ "$dut" -ge 0 ]
then then
echo "Board under test was found on bus $dut" echo "Board under test was found on bus $dut"
else else
......
fmcdac600m12b1chadds.sh
View file @ ad6ecf9e
#!/bin/bash #!/bin/bash
rmmod fmc_adc_100m14b 2> /dev/null rmmod fmc_adc_100m14b 2> /dev/null
rmmod zio 2> /dev/null rmmod zio 2> /dev/null
rmmod rawrabbit 2> /dev/null rmmod rawrabbit 2> /dev/null
rmmod spec 2> /dev/null rmmod spec 2> /dev/null
rmmod fmc 2> /dev/null rmmod fmc 2> /dev/null
rmmod cp210x 2>/dev/null
rmmod usbtmc 2>/dev/null
prg=$0 prg=$0
if [ ! -e "$prg" ]; then if [ ! -e "$prg" ]; then
...@@ -24,23 +20,19 @@ dir=$( ...@@ -24,23 +20,19 @@ dir=$(
) || exit ) || exit
prg=$dir/$(basename -- "$prg") || exit prg=$dir/$(basename -- "$prg") || exit
top=`echo "$prg" | sed 's/pts.*/pts\//'` top=`dirname -- "$prg"`
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-bus/kernel/fmc.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/spec-sw/kernel/spec.ko" "fw_name=../../$top/test/fmcdac600m12b1chadds/gateware/spec-init.bin-2012-12-14"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/zio/zio.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/kernel/fmc-adc-100m14b.ko" "gateware=../../$top/test/fmcdac600m12b1chadds/gateware/spec-fmc-adc-v4.0.bin"
insmod "$top/cp210x/cp210x.ko"
insmod "$top/software/fmc-bus/kernel/fmc.ko"
insmod "$top/software/spec-sw/kernel/spec.ko" "fw_name=../../$top/gateware/spec-init.bin-2012-12-14"
insmod "$top/software/fmc-adc-100m14b4cha-sw/zio/zio.ko"
insmod "$top/software/fmc-adc-100m14b4cha-sw/kernel/fmc-adc-100m14b.ko" "gateware=../../$top/gateware/spec-fmc-adc-v4.0.bin"
LOGDIR="$top/log_fmcdac600m12b1chadds" LOGDIR="$top/log_fmcdac600m12b1chadds"
mkdir -p "$LOGDIR" mkdir -p "$LOGDIR"
mkdir -p "$LOGDIR/eeprom" mkdir -p "$LOGDIR/eeprom"
mkdir -p "$LOGDIR/tmp"
serial=$1 serial=$1
...@@ -74,9 +66,7 @@ do ...@@ -74,9 +66,7 @@ do
echo "Test series run $nb_test out of $nb_test_limit" echo "Test series run $nb_test out of $nb_test_limit"
echo " " echo " "
sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 02 03 04 05 06 07 sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./python -l $LOGDIR 00 01 02 03 04 05 08 10 11 07
# sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 03 04 05 06 07
if [ "$nb_test" != "$nb_test_limit" ] if [ "$nb_test" != "$nb_test_limit" ]
then then
......
gateware/rtl/dds_core.vhd
View file @ ad6ecf9e
...@@ -17,10 +17,29 @@ entity dds_core is ...@@ -17,10 +17,29 @@ entity dds_core is
port ( port (
-- Clocks & resets -- Clocks & resets
-- SPEC boot clk
-- should be 62M5
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
-- CLK1OUT on FMCv2
-- FMC_CLK_LA0CC on FMCv3
-- connected to IC9 (AD9516)
-- should be 500M
clk_dds_i : in std_logic; clk_dds_i : in std_logic;
-- CLK1OUT on FMCv2
-- FMC_CLK_LA0CC on FMCv3
-- connected to IC9 (AD9516)
-- should be 125M
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
-- CLK2OUT on FMCv2
-- FMC_CLK on FMCv3
-- multiplied to 250M
clk_rf_i : in std_logic; clk_rf_i : in std_logic;
-- CLK0OUT
-- connected directly to DAC
clk_dac_i : in std_logic; clk_dac_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
...@@ -43,6 +62,7 @@ entity dds_core is ...@@ -43,6 +62,7 @@ entity dds_core is
pll_vcxo_function_o : out std_logic; pll_vcxo_function_o : out std_logic;
pll_vcxo_sdo_i : in std_logic; pll_vcxo_sdo_i : in std_logic;
pll_vcxo_status_i : in std_logic; pll_vcxo_status_i : in std_logic;
pll_vcxo_clk0_sel_o : out std_logic;
pll_sys_cs_n_o : out std_logic; pll_sys_cs_n_o : out std_logic;
pll_sys_ld_i : in std_logic; pll_sys_ld_i : in std_logic;
...@@ -814,6 +834,7 @@ begin -- behavioral ...@@ -814,6 +834,7 @@ begin -- behavioral
pll_vcxo_cs_n_o <= regs_out.gpior_pll_vcxo_cs_n_o; pll_vcxo_cs_n_o <= regs_out.gpior_pll_vcxo_cs_n_o;
pll_vcxo_function_o <= regs_out.gpior_pll_vcxo_function_o; pll_vcxo_function_o <= regs_out.gpior_pll_vcxo_function_o;
pll_vcxo_clk0_sel_o <= regs_out.gpior_pll_vcxo_ref_sel_o;
regs_in_local.gpior_pll_vcxo_status_n_i <= pll_vcxo_status_i; regs_in_local.gpior_pll_vcxo_status_n_i <= pll_vcxo_status_i;
regs_in_local.gpior_pll_vcxo_sdo_i <= pll_vcxo_sdo_i; regs_in_local.gpior_pll_vcxo_sdo_i <= pll_vcxo_sdo_i;
...@@ -983,11 +1004,11 @@ begin -- behavioral ...@@ -983,11 +1004,11 @@ begin -- behavioral
freq_meter2_u: gc_frequency_meter freq_meter2_u: gc_frequency_meter
generic map( generic map(
g_with_internal_timebase => true, g_with_internal_timebase => true,
g_clk_sys_freq => 125000000, g_clk_sys_freq => 62500000,
g_counter_bits => 28 g_counter_bits => 28
) )
port MAP( port MAP(
clk_sys_i => clk_ref_i, clk_sys_i => clk_sys_i,
clk_in_i => clk_rf_i, clk_in_i => clk_rf_i,
rst_n_i => rst_n_ref, rst_n_i => rst_n_ref,
pps_p1_i => '0', pps_p1_i => '0',
...@@ -998,14 +1019,12 @@ begin -- behavioral ...@@ -998,14 +1019,12 @@ begin -- behavioral
freq_meter1_u: gc_frequency_meter freq_meter1_u: gc_frequency_meter
generic map( generic map(
g_with_internal_timebase => true, g_with_internal_timebase => true,
g_clk_sys_freq => 125000000, g_clk_sys_freq => 62500000,
g_counter_bits => 28 g_counter_bits => 28
) )
port MAP( port MAP(
-- actually im going to change ref clk freq clk_sys_i => clk_sys_i,
-- but i dont want to measure it wiht slower clock clk_in_i => clk_ref_i,
clk_sys_i => clk_ref_i,
clk_in_i => clk_sys_i,
rst_n_i => rst_n_ref, rst_n_i => rst_n_ref,
pps_p1_i => '0', pps_p1_i => '0',
freq_o => meas_freq1, freq_o => meas_freq1,
...@@ -1015,13 +1034,11 @@ begin -- behavioral ...@@ -1015,13 +1034,11 @@ begin -- behavioral
freq_meter0_u: gc_frequency_meter freq_meter0_u: gc_frequency_meter
generic map( generic map(
g_with_internal_timebase => true, g_with_internal_timebase => true,
g_clk_sys_freq => 125000000, g_clk_sys_freq => 62500000,
g_counter_bits => 28 g_counter_bits => 28
) )
port MAP( port MAP(
-- actually im going to change ref clk freq clk_sys_i => clk_sys_i,
-- but i dont want to measure it wiht slower clock
clk_sys_i => clk_ref_i,
clk_in_i => clk_dac_i, clk_in_i => clk_dac_i,
rst_n_i => rst_n_ref, rst_n_i => rst_n_ref,
pps_p1_i => '0', pps_p1_i => '0',
...@@ -1032,13 +1049,12 @@ begin -- behavioral ...@@ -1032,13 +1049,12 @@ begin -- behavioral
freq_meter_trigg_u: gc_frequency_meter freq_meter_trigg_u: gc_frequency_meter
generic map( generic map(
g_with_internal_timebase => true, g_with_internal_timebase => true,
g_clk_sys_freq => 125000000, g_clk_sys_freq => 62500000,
g_counter_bits => 28 g_counter_bits => 28
) )
port MAP( port MAP(
-- actually im going to change ref clk freq
-- but i dont want to measure it wiht slower clock clk_sys_i => clk_sys_i,
clk_sys_i => clk_ref_i,
clk_in_i => trigger_i, clk_in_i => trigger_i,
rst_n_i => rst_n_ref, rst_n_i => rst_n_ref,
pps_p1_i => '0', pps_p1_i => '0',
......
gateware/rtl/dds_wb_slave.vhd
View file @ ad6ecf9e
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for DDS RF distribution WB Slave -- Title : Wishbone slave core for DDS RF distribution WB Slave
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : /home/gumas/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.vhd -- File : /home/gumas/projects/cti/pts/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb -- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
-- Created : Tue Aug 11 14:03:44 2015 -- Created : Fri Feb 1 09:37:20 2019
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -59,6 +59,7 @@ signal dds_gpior_adf_data_int : std_logic ; ...@@ -59,6 +59,7 @@ signal dds_gpior_adf_data_int : std_logic ;
signal dds_gpior_adc_sdi_int : std_logic ; signal dds_gpior_adc_sdi_int : std_logic ;
signal dds_gpior_adc_cnv_int : std_logic ; signal dds_gpior_adc_cnv_int : std_logic ;
signal dds_gpior_adc_sck_int : std_logic ; signal dds_gpior_adc_sck_int : std_logic ;
signal dds_gpior_pll_vcxo_ref_sel_int : std_logic ;
signal dds_pd_fifo_rst_n : std_logic ; signal dds_pd_fifo_rst_n : std_logic ;
signal dds_pd_fifo_in_int : std_logic_vector(15 downto 0); signal dds_pd_fifo_in_int : std_logic_vector(15 downto 0);
signal dds_pd_fifo_out_int : std_logic_vector(15 downto 0); signal dds_pd_fifo_out_int : std_logic_vector(15 downto 0);
...@@ -193,6 +194,7 @@ begin ...@@ -193,6 +194,7 @@ begin
dds_gpior_adc_sdi_int <= '0'; dds_gpior_adc_sdi_int <= '0';
dds_gpior_adc_cnv_int <= '0'; dds_gpior_adc_cnv_int <= '0';
dds_gpior_adc_sck_int <= '0'; dds_gpior_adc_sck_int <= '0';
dds_gpior_pll_vcxo_ref_sel_int <= '0';
dds_freq_hi_int <= "00000000000000000000000000000000"; dds_freq_hi_int <= "00000000000000000000000000000000";
dds_freq_hi_swb <= '0'; dds_freq_hi_swb <= '0';
dds_freq_hi_swb_delay <= '0'; dds_freq_hi_swb_delay <= '0';
...@@ -322,6 +324,7 @@ begin ...@@ -322,6 +324,7 @@ begin
dds_gpior_adc_sdi_int <= wrdata_reg(16); dds_gpior_adc_sdi_int <= wrdata_reg(16);
dds_gpior_adc_cnv_int <= wrdata_reg(17); dds_gpior_adc_cnv_int <= wrdata_reg(17);
dds_gpior_adc_sck_int <= wrdata_reg(18); dds_gpior_adc_sck_int <= wrdata_reg(18);
dds_gpior_pll_vcxo_ref_sel_int <= wrdata_reg(22);
end if; end if;
rddata_reg(0) <= dds_gpior_pll_sys_cs_n_int; rddata_reg(0) <= dds_gpior_pll_sys_cs_n_int;
rddata_reg(1) <= dds_gpior_pll_sys_reset_n_int; rddata_reg(1) <= dds_gpior_pll_sys_reset_n_int;
...@@ -345,7 +348,7 @@ begin ...@@ -345,7 +348,7 @@ begin
rddata_reg(19) <= regs_i.gpior_adc_sdo_i; rddata_reg(19) <= regs_i.gpior_adc_sdo_i;
rddata_reg(20) <= regs_i.gpior_fmc_present_i; rddata_reg(20) <= regs_i.gpior_fmc_present_i;
rddata_reg(21) <= regs_i.gpior_test_pll_ld_i; rddata_reg(21) <= regs_i.gpior_test_pll_ld_i;
rddata_reg(22) <= 'X'; rddata_reg(22) <= dds_gpior_pll_vcxo_ref_sel_int;
rddata_reg(23) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(25) <= 'X';
...@@ -1200,6 +1203,8 @@ begin ...@@ -1200,6 +1203,8 @@ begin
-- AD7980 Bitbanged Data In -- AD7980 Bitbanged Data In
-- FMC present -- FMC present
-- test clock PLL locked -- test clock PLL locked
-- IC26 clock select
regs_o.gpior_pll_vcxo_ref_sel_o <= dds_gpior_pll_vcxo_ref_sel_int;
-- extra code for reg/fifo/mem: PD ADC Test FIFO (test mode) -- extra code for reg/fifo/mem: PD ADC Test FIFO (test mode)
dds_pd_fifo_in_int(15 downto 0) <= regs_i.pd_fifo_data_i; dds_pd_fifo_in_int(15 downto 0) <= regs_i.pd_fifo_data_i;
dds_pd_fifo_rst_n <= rst_n_i; dds_pd_fifo_rst_n <= rst_n_i;
......
gateware/rtl/dds_wb_slave.wb
View file @ ad6ecf9e
...@@ -260,6 +260,19 @@ peripheral { ...@@ -260,6 +260,19 @@ peripheral {
type = BIT; type = BIT;
}; };
field {
name = "IC26 clock select";
prefix = "PLL_VCXO_REF_SEL";
description = "select input of clock mux IC24 (Si53340) \
low value selects CLK1 input (RF IN - input connector) \
high value selects CLK0 input (REF IN - clock generated by DAC) \
output of IC24 is connected to IC26 (AD9516) CLK input \
net is pulled down by the R80 on the PCB";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
}; };
......
gateware/rtl/dds_wbgen2_pkg.vhd
View file @ ad6ecf9e
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for DDS RF distribution WB Slave -- Title : Wishbone slave core for DDS RF distribution WB Slave
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : /home/gumas/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wbgen2_pkg.vhd -- File : /home/gumas/projects/cti/pts/fmcdac600m12b1chadds//gateware/rtl/dds_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb -- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
-- Created : Tue Aug 11 14:03:44 2015 -- Created : Fri Feb 1 09:37:20 2019
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -112,6 +112,7 @@ package dds_wbgen2_pkg is ...@@ -112,6 +112,7 @@ package dds_wbgen2_pkg is
gpior_adc_sdi_o : std_logic; gpior_adc_sdi_o : std_logic;
gpior_adc_cnv_o : std_logic; gpior_adc_cnv_o : std_logic;
gpior_adc_sck_o : std_logic; gpior_adc_sck_o : std_logic;
gpior_pll_vcxo_ref_sel_o : std_logic;
pd_fifo_wr_full_o : std_logic; pd_fifo_wr_full_o : std_logic;
pd_fifo_wr_empty_o : std_logic; pd_fifo_wr_empty_o : std_logic;
tune_fifo_rd_empty_o : std_logic; tune_fifo_rd_empty_o : std_logic;
...@@ -169,6 +170,7 @@ package dds_wbgen2_pkg is ...@@ -169,6 +170,7 @@ package dds_wbgen2_pkg is
gpior_adc_sdi_o => '0', gpior_adc_sdi_o => '0',
gpior_adc_cnv_o => '0', gpior_adc_cnv_o => '0',
gpior_adc_sck_o => '0', gpior_adc_sck_o => '0',
gpior_pll_vcxo_ref_sel_o => '0',
pd_fifo_wr_full_o => '0', pd_fifo_wr_full_o => '0',
pd_fifo_wr_empty_o => '0', pd_fifo_wr_empty_o => '0',
tune_fifo_rd_empty_o => '0', tune_fifo_rd_empty_o => '0',
......
gateware/syn/pts_fmcdds.xise
View file @ ad6ecf9e
This diff is collapsed.
gateware/top/spec_top.ucf
View file @ ad6ecf9e
...@@ -197,20 +197,20 @@ NET "fmc_prsnt_m2c_l_i" IOSTANDARD = LVCMOS25; ...@@ -197,20 +197,20 @@ NET "fmc_prsnt_m2c_l_i" IOSTANDARD = LVCMOS25;
# NET "sfp_rxn_i" LOC = C15; # NET "sfp_rxn_i" LOC = C15;
# NET "sfp_txp_o" LOC = B16; # NET "sfp_txp_o" LOC = B16;
# NET "sfp_txn_o" LOC = A16; # NET "sfp_txn_o" LOC = A16;
NET "sfp_mod_def1_b" LOC = C17; # NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def1_b" IOSTANDARD = LVCMOS25; # NET "sfp_mod_def1_b" IOSTANDARD = LVCMOS25;
NET "sfp_mod_def0_b" LOC = G15; # NET "sfp_mod_def0_b" LOC = G15;
NET "sfp_mod_def0_b" IOSTANDARD = LVCMOS25; # NET "sfp_mod_def0_b" IOSTANDARD = LVCMOS25;
NET "sfp_mod_def2_b" LOC = G16; # NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_mod_def2_b" IOSTANDARD = LVCMOS25; # NET "sfp_mod_def2_b" IOSTANDARD = LVCMOS25;
NET "sfp_rate_select_b" LOC = H14; # NET "sfp_rate_select_b" LOC = H14;
NET "sfp_rate_select_b" IOSTANDARD = LVCMOS25; # NET "sfp_rate_select_b" IOSTANDARD = LVCMOS25;
NET "sfp_tx_fault_i" LOC = A17; # NET "sfp_tx_fault_i" LOC = A17;
NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS25; # NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS25;
NET "sfp_tx_disable_o" LOC = F17; # NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_disable_o" IOSTANDARD = LVCMOS25; # NET "sfp_tx_disable_o" IOSTANDARD = LVCMOS25;
NET "sfp_los_i" LOC = D18; # NET "sfp_los_i" LOC = D18;
NET "sfp_los_i" IOSTANDARD = LVCMOS25; # NET "sfp_los_i" IOSTANDARD = LVCMOS25;
#################################################################################### ####################################################################################
# Misc # Misc
#################################################################################### ####################################################################################
...@@ -237,6 +237,8 @@ NET "sfp_los_i" IOSTANDARD = LVCMOS25; ...@@ -237,6 +237,8 @@ NET "sfp_los_i" IOSTANDARD = LVCMOS25;
# should be placed under delay chip # should be placed under delay chip
NET "dds_onewire_b" LOC = T11; NET "dds_onewire_b" LOC = T11;
NET "dds_onewire_b" IOSTANDARD = LVCMOS25; NET "dds_onewire_b" IOSTANDARD = LVCMOS25;
NET "dds_onewire_b" PULLUP;
...@@ -413,6 +415,9 @@ NET "dds_pll_vcxo_cs_n_o" IOSTANDARD = LVCMOS25; ...@@ -413,6 +415,9 @@ NET "dds_pll_vcxo_cs_n_o" IOSTANDARD = LVCMOS25;
NET "dds_pll_vcxo_sdo_i" LOC = V13; NET "dds_pll_vcxo_sdo_i" LOC = V13;
NET "dds_pll_vcxo_sdo_i" IOSTANDARD = LVCMOS25; NET "dds_pll_vcxo_sdo_i" IOSTANDARD = LVCMOS25;
NET "dds_pll_vcxo_clk0_sel_o" LOC = AA8;
NET "dds_pll_vcxo_clk0_sel_o" IOSTANDARD = LVCMOS25;
#################################################################### ####################################################################
############ WR CLK PLL ############ ############ WR CLK PLL ############
......
gateware/top/spec_top.vhd
View file @ ad6ecf9e
This diff is collapsed.
new_ad9516_pts_ad9510_clk.stp 0 → 100644
View file @ ad6ecf9e
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111101","7D"
"0011","00000001","01"
"0012","00000000","00"
"0013","00000110","06"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000100","04"
"0017","10110111","B7"
"0018","00000110","06"
"0019","00000000","00"
"001A","00000101","05"
"001B","00000000","00"
"001C","00000001","01"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001000","08"
"00F4","00001000","08"
"00F5","00001010","0A"
"0140","01000010","42"
"0141","01000011","43"
"0142","01000011","43"
"0143","01000011","43"
"0190","00000000","00"
"0191","10000000","80"
"0192","00000000","00"
"0193","01000100","44"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","10000000","80"
"0198","00000000","00"
"0199","01000100","44"
"019A","00000000","00"
"019B","00010001","11"
"019C","00110000","30"
"019D","00000000","00"
"019E","00100010","22"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00000000","00"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000001","01"
"01E1","00000001","01"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",10
"REF 2:",30.72
"VCO:",1500
"CLK:",10
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
ptsDacDDS.py
View file @ ad6ecf9e
...@@ -57,10 +57,12 @@ def run_test(testname, logname, card, test_path, serial, yes=False): ...@@ -57,10 +57,12 @@ def run_test(testname, logname, card, test_path, serial, yes=False):
sys.stdin = open('/dev/null') sys.stdin = open('/dev/null')
__builtins__.raw_input = pts_raw_input __builtins__.raw_input = pts_raw_input
mod = __import__(testname, globals(), locals(), []) mod = __import__(testname, globals(), locals(), [])
if (testname == "test06"): if (testname == "test07"):
card = mod.main(card, serial, default_directory=test_path) card = mod.main(card, serial, default_directory=test_path)
elif (testname == "test02"): elif (testname == "test02"):
card = mod.main(card, logname, default_directory=test_path) card = mod.main(card, logname, default_directory=test_path)
elif (testname == "test08"):
card = mod.main(card, logname, default_directory=test_path)
else: else:
card = mod.main(card, default_directory=test_path) card = mod.main(card, default_directory=test_path)
finally: finally:
......
ptsexcept.py 0 → 100644
View file @ ad6ecf9e
#! /usr/bin/env python
# coding: utf8
class PtsException(Exception):
pass
class PtsCritical(PtsException):
"""critical error, abort the whole test suite"""
pass
class PtsError(PtsException):
"""error, continue remaining tests in test suite"""
pass
class PtsUser(PtsException):
"""error, user intervention required"""
pass
class PtsWarning(PtsException):
"""warning, a cautionary message should be displayed"""
pass
class PtsInvalid(PtsException):
"""reserved: invalid parameters"""
class PtsNoBatch(PtsInvalid):
"""reserved: a suite was created without batch of tests to run"""
pass
class PtsBadTestNo(PtsInvalid):
"""reserved: a bad test number was given"""
pass
if __name__ == '__main__':
pass
ptsfiles/cp210x/Makefile deleted 100644 → 0
View file @ 99babf85
obj-m = cp210x.o
KVERSION = $(shell uname -r)
all:
make -C /lib/modules/$(KVERSION)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(KVERSION)/build M=$(PWD) clean
install:
cp cp210x.ko /lib/modules/$(KVERSION)/kernel/drivers/usb/serial/
ptsfiles/cp210x/cp210x.c deleted 100644 → 0
View file @ 99babf85
This diff is collapsed.
python/OneWireMaster.py 0 → 100644
View file @ ad6ecf9e
class OneWireMaster:
R_CSR=0x0
R_CDR=0x4
CSR_DAT_MSK =(1<<0)
CSR_RST_MSK =(1<<1)
CSR_OVD_MSK =(1<<2)
CSR_CYC_MSK =(1<<3)
CSR_PWR_MSK =(1<<4)
CSR_IRQ_MSK =(1<<6)
CSR_IEN_MSK =(1<<7)
CSR_SEL_OFS =8
CSR_SEL_MSK =(0xF<<8)
CSR_POWER_OFS =16
CSR_POWER_MSK =(0xFFFF<<16)
CDR_NOR_MSK =(0xFFFF<<0)
CDR_OVD_OFS =16
CDR_OVD_MSK =(0XFFFF<<16)
def __init__(self, reg_rd, reg_wr, base=0x0):
self._rd=reg_rd
self._wr=reg_wr
self.base = base
def slot(self, bit):
# request bit write
self.write_reg( self.R_CSR, self.CSR_CYC_MSK | (bit & self.CSR_DAT_MSK) )
# wait for completion
while(1):
stat = self.read_reg(self.R_CSR)
if not (stat&self.CSR_CYC_MSK):
break
# return the data
return (stat&self.CSR_DAT_MSK)
def reset(self):
# request bit write
self.write_reg( self.R_CSR, self.CSR_CYC_MSK | self.CSR_RST_MSK )
# wait for completion
while(1):
stat = self.read_reg(self.R_CSR)
if not (stat&self.CSR_CYC_MSK):
break
if (stat&self.CSR_DAT_MSK):
return False
else:
return True
def read_reg(self, reg):
return self._rd(self.base+reg)
def write_reg(self, reg, dat):
return self._wr(self.base+reg, dat)
def read_bit(self):
return self.slot(1)
def write_bit(self, bit):
written = self.slot(bit)
if written != bit:
print "Failed One wire write!"
return -1
else:
return 0;
def read_byte(self):
ret = 0
for i in xrange(8):
ret |= (self.read_bit()<<i)
return ret
def write_byte(self, byte):
ret = 0
for i in xrange(8):
ret |= self.write_bit( byte&0x1 )
byte = byte>>1
return ret
def read_block(self, bnr):
if bnr > 160:
print "Too long!"
return
ret = [0]*bnr
for i in xrange(bnr):
ret[i] = self.read_byte()
return ret
def write_block(self, dat):
if len(dat)> 160:
print "Too long!"
return
for d in dat:
self.write_byte(d)
def configure_dividers(self, clk_freq):
cdr_n = int(clk_freq*(5e-6)-1)
cdr_o = int(clk_freq*(1e-6)-1)
reg = (cdr_n&self.CDR_NOR_MSK) | (( cdr_o<<self.CDR_OVD_OFS)&self.CDR_OVD_MSK )
# print "Onewire divider values: CDR_N: %d, CDR_o:%d."% (cdr_n, cdr_o)
# print "Writing to register: 0x%x" % reg
self.write_reg(self.R_CDR, reg)
python/PAGE/Agilent33250A.py deleted 100644 → 0
View file @ 99babf85
This diff is collapsed.
python/PAGE/Generator.py deleted 100644 → 0
View file @ 99babf85
from Utilities import *
from Item import *
"""This class manages a generic waveform generator."""
class Generator(Item):
def get(self, what):
"""Get an attribute value. Supports Pyro4."""
return self.__getattribute__(what)
def set(self, what, how):
"""Set an attribute value. Supports Pyro4."""
self.__setattr__(what, how)
# this dictionary is used to map data types into function which can
# translate such type of data into something the generator can understand.
adaptDict = {}
def adaptKeys(self):
"""Returns all data types supported."""
return self.adaptDict.keys()
def adapt(self, wave, *args, **kwargs):
"""Adapt a wave to the generator"""
return self.adaptDict[type(wave)](wave, *args, **kwargs)
def __init__(self, *args, **kwargs):
Item.__init__(self, *args, **kwargs)
python/PAGE/Item.py deleted 100644 → 0
View file @ 99babf85
"""This class just represent an API item. An item is configurable and has two
methods, get and set, which actually wrap getattribute and setattr."""
class Item(object):
# these are the default values of the parameters used
#
# the key of the dictionary is the actual name of the parameter in the class
# the item is a list:
# 1. Name of the parameter
# 2. Description
# 3. Default value
# 4. Type (it's just an object, really)
_parameters = {}
def __init__(self, *args, **kwargs):
"""Create the object and loads alll the parameters from kwargs.
Look at _parameters for more information."""
self.parameters = dict(self._parameters)
for i in kwargs:
if i in self.parameters.keys():
self.parameters[i][2] = kwargs[i]
for i in self.parameters.keys():
self.__setattr__(i, self.parameters[i][2])
python/PAGE/PulseWaveform.py deleted 100644 → 0
View file @ 99babf85
import Waveform
from Utilities import *
from numpy import *
import Pyro4
import Pyro4.util
import sys
class PulseWaveform(Waveform.Waveform):
def get(self, what):
return self.__getattribute__(what)
def set(self, what, how):
self.__setattr__(what, how)
_parameters = {'frequency':['Frequency', 'Frequency of the pulse, in HZ', 1000, float],
'amplitude':['Amplitude', 'Amplitude of the pulse, in Vpp', 1, float],
'dc':['DC Compoment', 'DC component of the pulse, in Vpp', 0, float]}
def __init__(self, *args, **kwargs):
Waveform.Waveform.__init__(self, *args, **kwargs)
name = 'Pulse Waveform'
target = PulseWaveform
import commands
def launch():
g = target()
hn = commands.getoutput('hostname')
daemon=Pyro4.Daemon(host = hn)
myUri = daemon.register(g)
ns=Pyro4.locateNS()
ns.register("Pulse", myUri)
daemon.requestLoop()
if __name__ == '__main__':
launch()
\ No newline at end of file
python/PAGE/RemoteObject.py deleted 100644 → 0
View file @ 99babf85
import sys
import Pyro4
import Item
from Utilities import *
from numpy import *
"""This class represents a remote object, using Pyro4 framework.
All it needs is a URI."""
class RemoteObject(Item.Item, Pyro4.Proxy):
_parameters = {'uri': ['URI', 'Name of the service', '', str]}
def __init__(self, *args, **kwargs):
Item.Item.__init__(self, *args, **kwargs)
Pyro4.Proxy.__init__(self, uri = Pyro4.locateNS().lookup(self.uri))
name = 'Remote Object'
target = RemoteObject
python/PAGE/SineWaveform.py deleted 100644 → 0
View file @ 99babf85
import Waveform
from Utilities import *
from numpy import *
import Pyro4
import Pyro4.util
import sys
class SineWaveform(Waveform.Waveform):
def get(self, what):
return self.__getattribute__(what)
def set(self, what, how):
self.__setattr__(what, how)
_parameters = {'frequency':['Frequency', 'Frequency of the sinewave, in HZ', 1000, float],
'amplitude':['Amplitude', 'Amplitude of the sinewave, in Vpp', 1, float],
'dc':['DC Compoment', 'DC component of the sinewave, in Vpp', 0, float]}
def __init__(self, *args, **kwargs):
Waveform.Waveform.__init__(self, *args, **kwargs)
def generate(self, sampleRate, samples, nbits, fsr):
f = self.frequency
A = self.amplitude
C = self.dc
t = arange(samples, dtype=float)/sampleRate
s = A*sin(2*pi*f*t) +C
lsb = fsr/(2**nbits)
return (s/lsb).astype(int)
def scale(self, factor):
"""Multiply the frequency by factor."""
self.frequency *= factor
return self
name = 'Sine Waveform'
target = SineWaveform
import commands
def launch():
g = target()
hn = commands.getoutput('hostname')
daemon=Pyro4.Daemon(host = hn)
myUri = daemon.register(g)
ns=Pyro4.locateNS()
ns.register("Sine", myUri)
daemon.requestLoop()
if __name__ == '__main__':
launch()
python/PAGE/Sis33.py deleted 100644 → 0
View file @ 99babf85
This diff is collapsed.
python/PAGE/TTWaveform.py deleted 100644 → 0
View file @ 99babf85
import Waveform
from Utilities import *
from numpy import *
import Pyro4
import Pyro4.util
import sys
import commands
class TTWaveform(Waveform.Waveform):
def get(self, what):
return self.__getattribute__(what)
def set(self, what, how):
self.__setattr__(what, how)
_parameters = {'frequency':['Frequency (1)', 'Frequency of the first sinewave, in HZ', float(5e6), float],
'ratio':['Ratio', 'Ratio between the frequency of the second sinewave and the one', 6./5., float],
'amplitude':['Amplitude', 'Amplitude of each sinewave, in Vpp', 1., float],
'dc':['DC Compoment', 'DC component of the whole waveform, in Vpp', 0., float]}
def __init__(self, *args, **kwargs):
Waveform.Waveform.__init__(self, *args, **kwargs)
def generate(self, sampleRate, samples, nbits, fsr):
f1, f2 = self.frequency, self.frequency * self.ratio
A = self.amplitude
C = self.dc
t = arange(samples, dtype=float)/sampleRate
s = A*sin(2*pi*f1*t) +A*sin(2*pi*f2*t) +C
lsb = fsr/(2**nbits)
return (s/lsb).astype(int)
def scale(self, factor):
"""Multiply the frequency by factor"""
self.frequency *= factor
return self
name = 'Two Tones Waveform'
target = TTWaveform
def launch():
g = target()
hn = commands.getoutput('hostname')
daemon = Pyro4.Daemon(host = hn)
myUri = daemon.register(g)
ns=Pyro4.locateNS()
ns.register("TTSine", myUri)
daemon.requestLoop()
if __name__ == '__main__':
launch()
python/PAGE/Utilities.py deleted 100644 → 0
View file @ 99babf85
def Property(func):
return property(**func())
decodeDict = {'KHZ': 3, 'MHZ': 6, 'HZ':0, 'UHZ': -6, 'NHZ': 9,
'MV': -3, 'NV': -6, 'KV': 3, 'V':0,
'MVPP': -3, 'NVPP': -6, 'KVPP': 3, 'VPP':0}
def decode(values):
return float(values[0])* (10.**float(decodeDict[values[1].upper()]))
def parse(value, s):
if type(value) is str:
value = value.split(" ")
value[0] = float(value[0])
value = tuple(value)
if type(value) is tuple and len(value) == 1:
value = value[0]
if type(value) is not tuple:
value = (value, s)
return tuple(str(i) for i in value)
def prettyParameter(x, vx):
print 'Parameter %s is called %s.' % (x, vx[0])
print 'Description:', vx[1]
print 'Default value, in %s, is %s' % (repr(vx[3]), repr(vx[2]))
python/PAGE/Waveform.py deleted 100644 → 0
View file @ 99babf85
from numpy import array
from Item import *
"""This class represent a generic waveform."""
class Waveform(Item):
def get(self, what):
"""Get an attribute value. Supports Pyro4."""
return self.__getattribute__(what)
def set(self, what, how):
"""Set an attribute value. Supports Pyro4."""
self.__setattr__(what, how)
"""A waveform must provide this method.
Create a numeric array which represents the wave."""
def generate(self, nbits, frequency, samples, fsr):
return array([])
def __init__(self, *args, **kwargs):
Item.__init__(self, *args, **kwargs)
def getType(self):
return type(self)
python/PAGE/__init__.py deleted 100644 → 0
View file @ 99babf85
__author__="Federico"
__date__ ="$Aug 17, 2011 4:43:08 PM$"
# PAGE: Python ADC and GEnerators API
hasSis33 = False
import SineWaveform, TTWaveform, PulseWaveform
import Agilent33250A
import RemoteObject
try:
import Sis33
hasSis33 = True
except:
#print 'Error while loading Sis33 module, skipping it'
pass
waveforms = (RemoteObject, SineWaveform, TTWaveform)
generators = (Agilent33250A, RemoteObject)
if hasSis33:
adcs = (RemoteObject, Sis33)
else:
adcs = (RemoteObject, )
python/PendulumCNT91.py deleted 100644 → 0
View file @ 99babf85
# Copyright INCAA Computers, 2012
# Author: Bert Gooijer <bert.gooijer@incaacomputers.com>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
import os
class usbtmc:
def __init__(self, device):
print("Opening: %s" % device)
self.device = device
self.FILE = os.open(device, os.O_RDWR)
def write(self, command):
os.write(self.FILE, command)
def read(self):
return os.read(self.FILE, 4000)
def getName(self):
self.write("*IDN?")
return self.read()
def sendReset(self):
self.write("*RST")
def close(self):
os.close(self.FILE)
class PendulumCNT91:
def __init__(self, device):
self.meas = usbtmc(device)
self.name = self.meas.getName()
print self.name
def write(self, command):
self.meas.write(command)
def read(self):
return self.meas.read()
def reset(self):
self.meas.sendReset()
def close(self):
self.meas.close()
\ No newline at end of file
python/acq.sh
View file @ ad6ecf9e
...@@ -13,33 +13,49 @@ dir=$( ...@@ -13,33 +13,49 @@ dir=$(
) || exit ) || exit
prg=$dir/$(basename -- "$prg") || exit prg=$dir/$(basename -- "$prg") || exit
top=`echo "$prg" | sed 's/fmcdac600m12b1chadds.*/fmcdac600m12b1chadds\//'` top=`dirname -- "$prg"`
# echo $top
export PATH="\ export PATH="\
$top/software/fmc-adc-100m14b4cha-sw/tools:\ $top/../software/fmc-adc-100m14b4cha-sw/tools:\
$top/software/fmc-adc-100m14b4cha-sw/libtools:\ $top/../software/fmc-adc-100m14b4cha-sw/libtools:\
$PATH" $PATH"
# echo $PATH # remove old data
rm -f /tmp/data.bin
# prepare the FMC ID in a format used by fald-acq
fmcid=`printf "%02x00" $3`
# prepare the path to the FMC files
adcpath="/sys/bus/zio/devices/adc-100m14b-${fmcid}/"
# read current software trigger setting
swen=`cat ${adcpath}/cset0/trigger/sw-trg-enable`
if [ $swen -eq 0 ];
then
# enable the software trigger if it wasn't already
echo 1 > "${adcpath}/cset0/trigger/sw-trg-enable"
# seems that there must be considerable delay after this change
sleep 5
fi
# configure the acquisition
# b - samples before trigger
# a - samples after trigger
# r - range (1V or 10V)
# B - output binary location
fald-acq -b 0 -a $1 -r $2 -B /tmp/data.bin "0x${fmcid}" &
rm /tmp/data.bin # wait for the program to start
# echo "1"
tmp=`printf "%02x00" $3`
adcpath="/sys/bus/zio/devices/adc-100m14b-$tmp/"
echo 1 > "${adcpath}/cset0/trigger/sw-trg-enable"
# echo 1 > /sys/bus/zio/devices/adc-100m14b-0200/cset0/trigger/sw-trg-enable
# echo "2"
sleep 1 sleep 1
# echo "3"
fald-acq -b 0 -a $1 -r $2 -B /tmp/data.bin "0x${tmp}" & # manually trigger the acquisition
# echo "4"
sleep 2
# echo "5"
echo 1 > "${adcpath}/cset0/trigger/sw-trg-fire" echo 1 > "${adcpath}/cset0/trigger/sw-trg-fire"
# echo 1 > /sys/bus/zio/devices/adc-100m14b-0200/cset0/trigger/sw-trg-fire
# echo "6" # wait for the detached program to return
wait wait
# echo "7"
) )
python/ad9510.py deleted 100644 → 0
View file @ 99babf85
This diff is collapsed.
python/ad9510_lib.py deleted 100644 → 0
View file @ 99babf85
def WBGEN2_GEN_WRITE(value, offset, size):
return (((value) & ((1<<(size))-1)) << (offset))
def SDO_INACTIVE(val):
return WBGEN2_GEN_WRITE(val, 7, 1)
def LSB_FIRST(val):
return WBGEN2_GEN_WRITE(val, 6, 1)
def SOFT_RESET(val):
return WBGEN2_GEN_WRITE(val, 5, 1)
def LONG_INSTRUCTION(val):
return WBGEN2_GEN_WRITE(val, 4, 1)
def A_COUNTER(val):
return WBGEN2_GEN_WRITE(val, 0, 6)
def B_COUNTER_MSB(val):
return WBGEN2_GEN_WRITE(val, 0, 5)
def B_COUNTER_LSB(val):
return WBGEN2_GEN_WRITE(val, 0, 8)
def LOR_DEL(val):
return WBGEN2_GEN_WRITE(val, 5, 2)
def LOR_EN(val):
return WBGEN2_GEN_WRITE(val, 2, 1)
def PFD_POLARITY(val):
return WBGEN2_GEN_WRITE(val, 6, 1)
def PLL_MUX_ON_STATUS(val):
return WBGEN2_GEN_WRITE(val, 2, 4)
def CP_MODE(val):
return WBGEN2_GEN_WRITE(val, 0, 2)
def CP_CURRENT(val):
return WBGEN2_GEN_WRITE(val, 4, 3)
def RESET_R(val):
return WBGEN2_GEN_WRITE(val, 2, 1)
def RESET_N(val):
return WBGEN2_GEN_WRITE(val, 1, 1)
def RESET_ALL_CNTRS(val):
return WBGEN2_GEN_WRITE(val, 0, 1)
def B_BYPASS(val):
return WBGEN2_GEN_WRITE(val, 6, 1)
def PRESCALLER(val):
return WBGEN2_GEN_WRITE(val, 2, 3)
def POWER_DOWN(val):
return WBGEN2_GEN_WRITE(val, 0, 2)
def R_DIVIDER_MSB(val):
return WBGEN2_GEN_WRITE(val, 0, 6)
def R_DIVIDER_LSB(val):
return WBGEN2_GEN_WRITE(val, 0, 8)
def DIGIT_LOCK_DET_EN(val):
return WBGEN2_GEN_WRITE(val, 6, 1)
def DIGIT_LOCK_DET_WND(val):
return WBGEN2_GEN_WRITE(val, 5, 1)
def ANTIBACKSLASH_PLS_WDTH(val):
return WBGEN2_GEN_WRITE(val, 0, 2)
def DEL_BYPASS(val):
return WBGEN2_GEN_WRITE(val, 0, 1)
def RAMP_CAP(val):
return WBGEN2_GEN_WRITE(val, 3, 3)
def RAMP_CURR(val):
return WBGEN2_GEN_WRITE(val, 0, 3)
def FINE_DELAY(val):
return WBGEN2_GEN_WRITE(val, 1, 5)
def OUTPUT_LEVEL(val):
return WBGEN2_GEN_WRITE(val, 2, 2)
def CMOS_INV(val):
return WBGEN2_GEN_WRITE(val, 4, 1)
def LOGIC_SEL(val):
return WBGEN2_GEN_WRITE(val, 3, 1)
def CMOS_OUTPUT_LEVEL(val):
return WBGEN2_GEN_WRITE(val, 1, 2)
def CMOS_OUTPUT_POWER(val):
return WBGEN2_GEN_WRITE(val, 0, 1)
def CLKS_IN_PD(val):
return WBGEN2_GEN_WRITE(val, 5, 1)
def REFIN_PD(val):
return WBGEN2_GEN_WRITE(val, 4, 1)
def CLK_PLL_PD(val):
return WBGEN2_GEN_WRITE(val, 3, 1)
def CLK2_PD(val):
return WBGEN2_GEN_WRITE(val, 2, 1)
def CLK1_PD(val):
return WBGEN2_GEN_WRITE(val, 1, 1)
def SEL_CLK_IN(val):
return WBGEN2_GEN_WRITE(val, 0, 1)
def LOW_CYCLES(val):
return WBGEN2_GEN_WRITE(val, 4, 4)
def HIGH_CYCLES(val):
return WBGEN2_GEN_WRITE(val, 0, 4)
def BYPASS(val):
return WBGEN2_GEN_WRITE(val, 7, 1)
def NO_SYNC(val):
return WBGEN2_GEN_WRITE(val, 6, 1)
def FORCE(val):
return WBGEN2_GEN_WRITE(val, 5, 1)
def START_HL(val):
return WBGEN2_GEN_WRITE(val, 4, 1)
def PHASE_OFFSET(val):
return WBGEN2_GEN_WRITE(val, 0, 4)
def SET_FUNCTION_PIN(val):
return WBGEN2_GEN_WRITE(val, 5, 2)
def PD_SYNC(val):
return WBGEN2_GEN_WRITE(val, 4, 1)
def PD_ALL_REF(val):
return WBGEN2_GEN_WRITE(val, 3, 1)
def SYNC_REG(val):
return WBGEN2_GEN_WRITE(val, 2, 1)
def SYNC_SELECT(val):
return WBGEN2_GEN_WRITE(val, 1, 1)
def SYNC_ENABLE(val):
return WBGEN2_GEN_WRITE(val, 0, 1)
def UPDATE_REGISTERS(val):
return WBGEN2_GEN_WRITE(val, 0, 1)
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connections = { 'raw_dac' : 1,
'ref_clk' : 2,
'beam_clk' : 3,
'pulse_out' : 4 }
\ No newline at end of file
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# -*- coding: utf-8 -*-
__author__ = "Johannes Hölzl <johannes.hoelzl@gmx.de>"
__license__ = "GNU LGPL"
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...@@ -5,7 +5,7 @@ import array ...@@ -5,7 +5,7 @@ import array
import struct import struct
import os import os
lib = cdll.LoadLibrary(os.path.dirname(__file__) + "/libipmi/libipmi.so") lib = cdll.LoadLibrary(os.path.dirname(__file__) + "/../software/fmc-bus/tools/libipmi/libipmi.so")
class c_CommonHeader(Structure): class c_CommonHeader(Structure):
_fields_ = [ _fields_ = [
......
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