home.md

@@ -2,13 +2,11 @@
 
 ## Project description
 
-The FmcAdc500M14b4cha is a 4-channel 500 MSPS 14 bit ADC card in FMC (FPGA Mezzanine Card, VITA 57.1) format using a High Pin-Count (HPC) connector. The module has 4 DC-coupled input channels with 50 Ω input impedance.
+The **FMC ADC 500M 14b 4CHA** is a 4-channel 500 MSPS 14 bit ADC card in FMC (FPGA Mezzanine Card, VITA 57.1) format using a High Pin-Count (HPC) connector. The module has 4 DC-coupled input channels with 50 Ω input impedance.
 
-**Below is only a template.
-Please update using the [recommended setup and usage guide](https://www.ohwr.org/project/ohr-support/wikis/Administrator-guide#recommended-setup-usage)**
+![FMC_ADC_500M_14b_4cha](uploads/451aac884ddeb7cf02bb22a9b3c526fd/FMC_ADC_500M_14b_4cha.png)
 
-![](https://ohwr.org/erikvanderbij/template/uploads/23a127884e2820d707e58c6119cde69d/spec_v1.1_top.JPG)  
-**SPEC 1.1 first prototype**
+**FMC ADC 500M 14b 4CHA, Hardware Rev C 2020**
 
 ## Specifications
 
@@ -35,28 +33,21 @@ Please update using the [recommended setup and usage guide](https://www.ohwr.org
 |FMC EEPROM|24LC64, as per VITA 57.1|
 |Power Consumption| specified as < 11&nbsp;W|
 
+**Block diagram**
+
+![FMCADC500M14b4cha_system_block_v3](uploads/0b6d9d0142d53c24ffe302ea833c1e38/FMCADC500M14b4cha_system_block_v3.png)
 
 **Notes:**
 
-  - The following features should be controllable by software:
-      - Input signal range, coupling, termination and offset adjustment
-      - Self-calibration
-      - Sampling clock selection
-      - Direction of external trigger in/out
-      - ADC configuration and status
-  - The offset adjustment must not clip the signal at the highest range
-    (+/- 5V). That is why the "max input signal amplitude" has been
-    specified as 10V, even though the selection of signal ranges only
-    goes up to 5V. This way, a +10V pulse with -5V offset could still be
-    digitised without clipping.
-  - The sampling clock should be derived from a voltage-controllable
-    125MHz clock source, controlled via an SPI DAC.
-  - A copy of the 125MHz clock source should be available on the FMC
-    connector pins.
+  - The ADC is the ADS54J54 (Texas Instruments)
+  - All clocks are generated by the Si5394 (Silicon Labs). The device has a working configuration during start-up, but can also be programmed during operation.
+  - Optional synchronization to external clock source
+  - DC/DC converters can be synchronized to a frequency generated by the FPGA
 
 ## Project information
 
-  - [Available documentation](Documents)
+  - [Clock configuration (Si5394)](clock_config)
+  - [ADC configuration (ADS54J54)](adc_config)
   - [Design reviews](Design reviews)
 
 ## Contacts