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|**Parameter**|**Value**|
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|PCB format|VITA 57.1 FMC HPC (single width, ruggedized)|
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| Vadj voltage | 1.8 V with protection if Vadj > 2.1 V |
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|Connectors|SMA|
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|Sampling Rate|500 MSPS|
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|Input Signal Type|single-ended|
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| ... | ... | @@ -88,4 +89,4 @@ This project is licensed under **CERN Open Hardware Licence v2** ([CERN-OHL-S](h |
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---
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03 May 2021 |
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20 May 2022 |
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