|
|
# Prepare a ISE project
|
|
|
|
|
|
Generate wb files with wbgen2 tool (see ohwr wbgen2
|
|
|
project)
|
|
|
|
|
|
xserra@pc208:<sub>/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/adc/wb\_gen\></sub>/project/wbgen2/wbgen2
|
|
|
--lang=vhdl --vo=fmc\_adc\_18b\_400ks\_csr.vhd
|
|
|
--doco=fmc\_adc\_18b\_400ks\_csr.htm ./fmc\_adc\_18b\_400ks\_csr.wb
|
|
|
|
|
|
Fetch the needed files:
|
|
|
|
|
|
xserra@pc208:<sub>/projects\>
|
|
|
cd</sub>/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn/
|
|
|
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn\>
|
|
|
hdlmake -f
|
|
|
INFO: Fetching needed modules.
|
|
|
\------------------
|
|
|
INFO: Fetching module:
|
|
|
git:https://www.ohwr.org/hdl-core-lib/gn4124-core.git \[parent:
|
|
|
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn\]
|
|
|
INFO: \[git\] Fetching to
|
|
|
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/ip\_cores
|
|
|
Cloning into gn4124-core...
|
|
|
remote: Counting objects: 3432, done.
|
|
|
remote: Compressing objects: 100% (1587/1587), done.
|
|
|
remote: Total 3432 (delta 1850), reused 3193 (delta 1718)
|
|
|
Receiving objects: 100% (3432/3432), 14.49 MiB | 8.27 MiB/s, done.
|
|
|
Resolving deltas: 100% (1850/1850), done.
|
|
|
\------------------
|
|
|
INFO: Fetching module:
|
|
|
git:https://www.ohwr.org/hdl-core-lib/ddr3-sp6-core.git \[parent:
|
|
|
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn\]
|
|
|
INFO: \[git\] Fetching to
|
|
|
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/ip\_cores
|
|
|
Cloning into ddr3-sp6-core...
|
|
|
remote: Counting objects: 1971, done.
|
|
|
remote: Compressing objects: 100% (654/654), done.
|
|
|
remote: Total 1971 (delta 1358), reused 1837 (delta 1264)
|
|
|
Receiving objects: 100% (1971/1971), 6.61 MiB | 2.78 MiB/s, done.
|
|
|
Resolving deltas: 100% (1358/1358), done.
|
|
|
\------------------
|
|
|
INFO: Fetching module:
|
|
|
git:https://www.ohwr.org/hdl-core-lib/general-cores.git \[parent:
|
|
|
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn\]
|
|
|
INFO: \[git\] Fetching to
|
|
|
/home/xserra/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/ip\_cores
|
|
|
Cloning into general-cores...
|
|
|
remote: Counting objects: 3982, done.
|
|
|
remote: Compressing objects: 100% (2714/2714), done.
|
|
|
remote: Total 3982 (delta 2514), reused 2036 (delta 1188)
|
|
|
Receiving objects: 100% (3982/3982), 9.81 MiB | 3.93 MiB/s, done.
|
|
|
Resolving deltas: 100% (2514/2514), done.
|
|
|
|
|
|
Generate ise project:
|
|
|
|
|
|
Before generating ise project, it has to be checked if environmental
|
|
|
variable PATH includes the following directions:
|
|
|
:/homelocal/Xilinx//14.7/ISE\_DS/ISE/bin/lin64/:/homelocal/Xilinx//14.7/ISE\_DS/ISE/bin/lin64/
|
|
|
|
|
|
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn\> echo
|
|
|
$PATH
|
|
|
PATH=/homelocal/sicilia/archiving/bin:/homelocal/sicilia/bin:/homelocal/sicilia/ds:/homelocal/sicilia/bin:/homelocal/sicilia/local/bin:/homelocal/sicilia/blissadm/bin:/homelocal/sicilia/blissadm/local/bin:/usr/NX/bin:/usr/lib64/mpi/gcc/openmpi/bin:/usr/local/bin:/usr/bin:/bin:/usr/bin/X11:/usr/X11R6/bin:/usr/games:/usr/lib/mit/bin:/usr/lib/mit/sbin
|
|
|
|
|
|
If they are not included, they must be be added:
|
|
|
|
|
|
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn\>
|
|
|
PATH=$PATH:/homelocal/Xilinx//14.7/ISE\_DS/ISE/bin/lin64/:/homelocal/Xilinx//14.7/ISE\_DS/ISE/bin/lin64/
|
|
|
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn\>
|
|
|
export PATH
|
|
|
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn\> echo
|
|
|
$PATH
|
|
|
PATH=/homelocal/sicilia/archiving/bin:/homelocal/sicilia/bin:/homelocal/sicilia/ds:/homelocal/sicilia/bin:/homelocal/sicilia/local/bin:/homelocal/sicilia/blissadm/bin:/homelocal/sicilia/blissadm/local/bin:/usr/NX/bin:/usr/lib64/mpi/gcc/openmpi/bin:/usr/local/bin:/usr/bin:/bin:/usr/bin/X11:/usr/X11R6/bin:/usr/games:/usr/lib/mit/bin:/usr/lib/mit/sbin:/homelocal/Xilinx//14.7/ISE\_DS/ISE/bin/lin64/:/homelocal/Xilinx//14.7/ISE\_DS/ISE/bin/lin64/
|
|
|
|
|
|
And finally the ise project can be created:
|
|
|
|
|
|
xserra@pc208:~/project/em2/FPGA/fmc-adc-400k18b4cha/hdl/spec/syn\>
|
|
|
hdlmake --ise-proj
|
|
|
INFO: Generating/updating ISE
|
|
|
projectbin:/usr/bin/X11:/usr/X11R6/bin:/usr/games:/usr/lib/mit/bin:/usr/lib/mit/sbin:/homelocal/Xilinx//14.7/ISE\_DS/ISE/bin/lin64/:/homelocal/Xilinx//14.7/ISE\_DS/ISE/bin/lin64/
|
|
|
|
|
|
My Personal setting on ISE (version 14.7):
|
|
|
|
|
|
with a mouse right botton click on the project structure, uncheck Manual
|
|
|
Compilation Order.
|
|
|
|
|
|
Set the proper top module:
|
|
|
|
|
|
Do a mouse right botton click on file spec\_top\_fmc\_18b400ks.vhd in
|
|
|
design tree of the project. Then click on set as Top Module, and accept
|
|
|
the warning.
|
|
|
|
|
|
Set to generate bin file:
|
|
|
|
|
|
Select the top file and in the processes subwindow select Generate
|
|
|
Programing File. Do a mouse right botton and click on Process
|
|
|
Properties... ,
|
|
|
|
|
|
Then check the option -g Binary: and click OK.
|
|
|
|
|
|
Compile the project.
|
|
|
|
|
|
Select the top file and in the processes subwindow select Generate
|
|
|
Programing File and do a double click.
|
|
|
|
|
|
|
|
|
|
|
|
### Files
|
|
|
* [index.png](/uploads/737346fae8f88add3babac2fc54f55fc/index.png)
|
|
|
* [index2.png](/uploads/7b464891a74982b7bffcd67555e6fd42/index2.png)
|
|
|
* [index3.png](/uploads/4b232c6409bafdc9083306c12c29e8e4/index3.png)
|
|
|
* [index4.png](/uploads/09db17f93f9d27dd1a4a1b66a6ca81e4/index4.png) |
|
|
\ No newline at end of file |