Optimize clock distribution
Few suggestions concerning clock distribution:
IC31: I would use the remaining LTC6951 outputs instead of splitting the 125 MHz oscillator output (remove IC31). Reasons:
- more flexibility in output clock selection (e.g. can have 10 MHz/100 MHz out instead of fixed 125 MHz, which is not a popular frequency in test&measurement).
- easier phase alignment for WR (we can use internal LTC6951 sync just to make sure the outputs start at the same phase, without caring at all about the PLL ref-to-out latency and lock to the 125 MHz provided by the LTC6951, regardless of the LTC6951 insertion delay).
- one less chip in BOM.
IC33/IC36: why do we need active CML->LVPECL translation? The input of HMCAD1511 has quite wide common mode range (0.3 ... Vdd-0.3 V). How about using AC-coupled 100 Ohm termination + bias network on CLKP?
- two less chips
- less additive jitter (not really a concern given the spec of the board, but...)