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FMC ADC 100M 14b 4cha - Testing
Commit 81384105 authored by Matthieu Cattin's avatar Matthieu Cattin
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svec_test01: Finish ddr access test, better error handling.

parent a172e8aa
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test/fmcadc100m14b4cha/python/svec_test01.py
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......@@ -26,7 +26,8 @@ from fmc_adc import *
"""
test01: Test mezzanines (all peripherals, 1-wire, i2c, spi, etc...)
svec_test01: Test mezzanines (all peripherals, 1-wire, i2c, spi, etc...)
Requires a pps pulse on trigger inputs.
"""
def main (default_directory='.'):
......@@ -97,7 +98,7 @@ def main (default_directory='.'):
for i in range(2):
try:
print('\n-------------------------------------------------------------')
print('[FMC slot %d]'%(i+1))
print('[FMC slot %d]\n'%(i+1))
# 1-wire
fmc[i].print_unique_id()
fmc[i].print_temp()
......@@ -107,13 +108,14 @@ def main (default_directory='.'):
periph_addr = fmc[i].sys_i2c_scan()
if(0 == len(periph_addr)):
error[i] = "No peripheral detected on system management I2C bus"
continue
if(1 != len(periph_addr)):
error[i] = "Signal integrity problem detected on system management I2C bus, %d devices detected instead of 1" % len(periph_addr)
if(EEPROM_ADDR != periph_addr[0]):
error[i] = "Wrong device mounted on system management I2C bus or soldering issues, address is:0x%.2X expected:0x%.2X" % (periph_addr[0],EEPROM_ADDR)
continue
# LEDs
"""
print('\nBlinking LEDs')
for j in range(3):
fmc[i].trig_led(1)
......@@ -122,30 +124,33 @@ def main (default_directory='.'):
fmc[i].trig_led(0)
fmc[i].acq_led(0)
time.sleep(.5)
"""
# i2c bus
periph_addr = fmc[i].i2c_scan()
if(0 == len(periph_addr)):
error[i] = 'No peripheral detected on I2C bus'
continue
if(1 != len(periph_addr)):
error[i] = 'Signal integrity problem detected on I2C bus, %d devices detected instead of 1'%(len(periph_addr))
continue
if(SI570_ADDR != periph_addr[0]):
error[i] = 'Wrong device mounted on I2C bus, address is:0x%.2X expected:0x%.2X'%(periph_addr[0],SI570_ADDR)
continue
# CSR
#fmc[i].print_adc_core_config()
fmc[i].print_adc_core_config()
# LTC2174 (SPI)
# LTC2174 (SPI, serdes)
fmc[i].testpat_en(TEST_PATTERN)
pattern = fmc[i].get_testpat()
if(TEST_PATTERN != pattern):
print('pattern:%.4X read:%.4X')%(TEST_PATTERN, pattern)
raise PtsError('Cannot access LTC2174 ADC through SPI')
error[i] = 'Cannot access LTC2174 ADC through SPI'
continue
fmc[i].print_adc_regs()
if(0 == fmc[i].get_serdes_sync_stat()):
print('SerDes are not synchronised')
raise PtsError('SerDes are not synchronised')
error[i] = 'SerDes are not synchronised'
continue
else:
print "SerDes are synchronised.\n"
print "Check received data."
......@@ -158,6 +163,7 @@ def main (default_directory='.'):
if((TEST_PATTERN<<2) != adc_value):
print('[Channel %d] Error: value mismatch!'%(j))
error[i] = '[Channel %d] LTC2174 test pattern error: value mismatch!'%(j)
continue
# External trigger
# hw trig, rising edge, external, sw disable, no delay
......@@ -172,27 +178,29 @@ def main (default_directory='.'):
print "Wait for trigger."
time.sleep(1.1)
if('WAIT_TRIG' == fmc[i].get_acq_fsm_state()):
raise PtsError('Acquisition FSM state : %s' % fmc[i].get_acq_fsm_state())
error[i] = 'Acquisition FSM state : %s' % fmc[i].get_acq_fsm_state()
continue
else:
print('The external trigger input is working fine.')
# DDR access
print('\nTest DDR access')
print('Read DDR')
ddr_data_rd = fmc[i].get_data(0x0, 15)
ddr_data_rd = fmc[i].get_data(0x0, 16, raw=True)
print('Write DDR')
ddr_data_wr = range(10)
ddr_data_wr = range(8)
fmc[i].put_data(0x0, ddr_data_wr)
ddr_data_wr.extend([0x0]*5)
ddr_data_wr.extend([0x0]*8)
print('Read DDR')
ddr_data_rdb = fmc[i].get_data(0x0, 15)
ddr_data_rdb = fmc[i].get_data(0x0, 16, raw=True)
print('addr: read: written: read back:')
for j in range(len(ddr_data_rd)):
print('%.3d 0x%.8x 0x%.8x 0x%.8x'%(j, ddr_data_rd[j], ddr_data_wr[j], ddr_data_rdb[j]))
ddr_data_exp = ddr_data_wr[0:8] + ddr_data_rd[8:16]
print('addr: read: written: read back expected:')
for j in range(len(ddr_data_rd)):
print('%.3d 0x%.8x 0x%.8x 0x%.8x 0x%.8x'%(j, ddr_data_rd[j], ddr_data_wr[j], ddr_data_rdb[j], ddr_data_exp[j]))
if ddr_data_rdb != ddr_data_exp:
error[i] = 'Error in ddr access'
continue
except FmcAdc100mOperationError as e:
raise PtsError("Mezzanine %d onewire test failed: %s" % (i+1, e))
......@@ -203,10 +211,14 @@ def main (default_directory='.'):
end_test_time = time.time()
print "[SVEC] Test%02d elapsed time: %.2f seconds\n" % (TEST_NB, end_test_time-start_test_time)
if(error[0] != ''):
raise PtsError('[FMC slot 1]' + error[0])
if(error[1] != ''):
raise PtsError('[FMC slot 2]' + error[1])
err_s = ''
if (error[0] != ''):
err_s = '[FMC slot 1]' + error[0] + '\n'
if (error[1] != ''):
err_s += '[FMC slot 2]' + error[1]
if (err_s != ''):
raise PtsError(err_s)
bus.vv_close()
......
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