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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
Commits
182fe53c
Commit
182fe53c
authored
May 09, 2012
by
Matthieu Cattin
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Modify UTC and IRQ cores functions to use the dictonary register map.
UTC tag read is still to be modified.
parent
dea99e37
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1 changed file
with
37 additions
and
18 deletions
+37
-18
fmc_adc_spec.py
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
+37
-18
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test/fmcadc100m14b4cha/python/fmc_adc_spec.py
View file @
182fe53c
...
...
@@ -235,28 +235,33 @@ class CFmcAdc100mSpec:
def
set_utc_time
(
self
):
current_time
=
time
.
time
()
utc_seconds
=
int
(
current_time
)
self
.
utc_core
.
wr_reg
(
self
.
UTC_CORE_
SECONDS
,
utc_seconds
)
self
.
set_reg
(
self
.
utc_core
,
UTC_CORE_REGS
,
SECONDS
,
utc_seconds
)
utc_coarse
=
int
((
current_time
-
utc_seconds
)
/
8E-9
)
self
.
utc_core
.
wr_reg
(
self
.
UTC_CORE_
COARSE
,
utc_coarse
)
return
curent_time
self
.
set_reg
(
self
.
utc_core
,
UTC_CORE_REGS
,
COARSE
,
utc_coarse
)
return
cur
r
ent_time
# Returns UTC seconds counter value
def
get_utc_second_cnt
(
self
):
return
self
.
utc_core
.
rd_reg
(
self
.
UTC_CORE_
SECONDS
)
return
self
.
get_reg
(
self
.
utc_core
,
UTC_CORE_REGS
,
SECONDS
)
# Set UTC seconds counter
def
set_utc_second_cnt
(
self
,
value
):
self
.
utc_core
.
wr_reg
(
self
.
UTC_CORE_
SECONDS
,
value
)
return
self
.
utc_core
.
rd_reg
(
self
.
UTC_CORE_
SECONDS
)
self
.
set_reg
(
self
.
utc_core
,
UTC_CORE_REGS
,
SECONDS
,
value
)
return
self
.
get_reg
(
self
.
utc_core
,
UTC_CORE_REGS
,
SECONDS
)
# Returns UTC coarse counter value
def
get_utc_coarse_cnt
(
self
):
return
self
.
utc_core
.
rd_reg
(
self
.
UTC_CORE_
COARSE
)
return
self
.
get_reg
(
self
.
utc_core
,
UTC_CORE_REGS
,
COARSE
)
# Set UTC coarse counter
def
set_utc_coarse_cnt
(
self
,
value
):
self
.
utc_core
.
wr_reg
(
self
.
UTC_CORE_COARSE
,
value
)
return
self
.
utc_core
.
rd_reg
(
self
.
UTC_CORE_COARSE
)
self
.
set_reg
(
self
.
utc_core
,
UTC_CORE_REGS
,
COARSE
,
value
)
return
self
.
get_reg
(
self
.
utc_core
,
UTC_CORE_REGS
,
COARSE
)
###########################################################################
########## Code to review ##########
###########################################################################
# Returns last trigger event time-tag
def
get_utc_trig_tag
(
self
):
...
...
@@ -326,41 +331,50 @@ class CFmcAdc100mSpec:
return
self
.
tag_end
###########################################################################
########## Code to review ##########
###########################################################################
#======================================================================
# Interrupt controller core
# Set IRQ enable mask
def
set_irq_en_mask
(
self
,
mask
):
self
.
irq_controller
.
wr_reg
(
self
.
IRQ_CTRL_
EN_MASK
,
mask
)
return
self
.
irq_controller
.
rd_reg
(
self
.
IRQ_CTRL_
EN_MASK
)
self
.
set_reg
(
self
.
irq_controller
,
IRQ_CONTROLLER_REGS
,
EN_MASK
,
mask
)
return
self
.
get_reg
(
self
.
irq_controller
,
IRQ_CONTROLLER_REGS
,
EN_MASK
)
# Get IRQ enable mask
def
get_irq_en_mask
(
self
):
return
self
.
irq_controller
.
rd_reg
(
self
.
IRQ_CTRL_
EN_MASK
)
return
self
.
get_reg
(
self
.
irq_controller
,
IRQ_CONTROLLER_REGS
,
EN_MASK
)
# Returns multiple IRQ status
def
get_irq_mult
(
self
):
return
self
.
irq_controller
.
rd_reg
(
self
.
IRQ_CTRL_MULT
)
return
self
.
get_reg
(
self
.
irq_controller
,
IRQ_CONTROLLER_REGS
,
MULTI_IRQ
)
# Clears multiple IRQ status
def
clear_irq_mult
(
self
,
irq
):
self
.
irq_controller
.
wr_reg
(
self
.
IRQ_CTRL_MULT
,
irq
)
return
self
.
irq_controller
.
rd_reg
(
self
.
IRQ_CTRL_MULT
)
self
.
set_reg
(
self
.
irq_controller
,
IRQ_CONTROLLER_REGS
,
MULTI_IRQ
,
irq
)
return
self
.
get_reg
(
self
.
irq_controller
,
IRQ_CONTROLLER_REGS
,
MULTI_IRQ
)
# Returns IRQ source
def
get_irq_source
(
self
):
return
self
.
irq_controller
.
rd_reg
(
self
.
IRQ_CTRL_
SRC
)
return
self
.
get_reg
(
self
.
irq_controller
,
IRQ_CONTROLLER_REGS
,
SRC
)
# Clears IRQ source
def
clear_irq_source
(
self
,
irq
):
self
.
irq_controller
.
wr_reg
(
self
.
IRQ_CTRL_
SRC
,
irq
)
return
self
.
irq_controller
.
rd_reg
(
self
.
IRQ_CTRL_
SRC
)
self
.
set_reg
(
self
.
irq_controller
,
IRQ_CONTROLLER_REGS
,
SRC
,
irq
)
return
self
.
get_reg
(
self
.
irq_controller
,
IRQ_CONTROLLER_REGS
,
SRC
)
#======================================================================
# Data acquisition (DMA transfer)
###########################################################################
########## Code to review ##########
###########################################################################
# Make a DMA transfer
# carrier_addr and length are in bytes
def
get_data
(
self
,
carrier_addr
,
length
):
...
...
@@ -429,3 +443,8 @@ class CFmcAdc100mSpec:
print
(
'IRQ source :
%.4
X'
)
%
self
.
get_irq_source
()
acq_end
=
1
print
(
'ACQ finished!'
)
###########################################################################
########## Code to review ##########
###########################################################################
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