the order of the lines connecting the ADC and the FPGA must be changed
For now, we've got the access to only two out of the four channels of the ADC. It is because ADC uses the fast serial interface, where all the lines must be connected to the one half of the bank (this is the set of outputs and it's fixed in FPGA) for the proper synchronization. For now, because channel one and channel two are connected to other half of BANK0 than the remaining lines (including the DCO-clock line, and the FR-synchronization line), there is no way to synchronize the SERDESes and those channels are unavailable. This information is valid for the SP605 Xilinx spartan kit as well as in case of our carriers. To make the boards fully compatible with the FMC standard, all the data output lines must be connected to the LA02 ... LA16, and the clock outputs (DCO & FR) must be connected to the LA00_CC and LA01_CC (all of them belong to the same half of BANK0).