Sundance suggested a possible reason for the (already low enough) temperature drift. This suggestion may need to be worked out and may be used in a future version of the design.

I kept thinking that the gain error drifts for BOTH ADC and DAC are an order of magnitude lower on the 1V0 range, but also that the ADC and DAC error drifts are almost identical.
Logically this means the drift must be in a component which is common to both ADC and DAC, and which is part of the gain setting circuit.
A look at the schematic and the obvious candidate is the photomos relays, which are AQY221N3M.
The data sheet for these says the on resistance is typically 5.5R, however there is a temperature dependency graph, which shows the on resistance varies from about 4R to 7.5R over the range 0 to 70 degrees.
Given the low impedance of the rest of this part of the circuit, that drift easily accounts for the measured 1% error drifts, and will completely dominate any drift in the precision resistors.
Panasonic make a lower resistance version AQY221R2M with resistance drift from about 0.5R to 1.5R (it is a small graph) over 0 to 70 degrees, but it has much higher capacitance at 14pF (instead of 1.1pF), which will probably effect the high frequency response.
While this might be worth a simple trial, the loss of high frequency response may make it unusable, even though I am fairly sure it would greatly improve the ADC and DAC gain temperature drift.

Best regards
Steve

Please refer to the measurements reports
https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis/Documents/2017-and-2018-Integration-and-Measurement-results