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mcattin authored
Hold sys reset until sys clock pll is locked, LED monstable reset from sys reset, add false path for ddr calib done in ucf. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@49 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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