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FMC ADC 100M 14b 4cha - Gateware
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Opened Apr 28, 2016 by Dimitris Lampridis@dlampridis
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Discipline the ADC sampling clock with WR

Discipline the 100MHz sampling clock with WR, in order to have multiple ADCs with synchonized sampling.

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Reference: project/fmc-adc-100m14b4cha-gw#11