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FMC ADC 100M 14b 4cha - Gateware
Commit f2c83354 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: bring testbenches up to date with latest modifications

parent c5f1f0c6
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Showing with 59 additions and 49 deletions
hdl/spec/testbench/top/gn4124_bfm/gn4124_bfm.svh
View file @ f2c83354
......@@ -230,15 +230,15 @@ endinterface
`define GENNUM_WIRE_SPEC_PINS(IF_NAME) \
.L_RST_N (IF_NAME.rst_n),\
.L_CLKp (IF_NAME.lclk_p),\
.L_CLKn (IF_NAME.lclk_n),\
// .L_CLKp (IF_NAME.lclk_p),\
// .L_CLKn (IF_NAME.lclk_n),\
.p2l_clkp (IF_NAME.p2l_clk_p),\
.p2l_clkn (IF_NAME.p2l_clk_n),\
.p2l_data (IF_NAME.p2l_data),\
.p2l_dframe (IF_NAME.p2l_dframe),\
.p2l_valid (IF_NAME.p2l_valid),\
.p2l_rdy (IF_NAME.p2l_rdy),\
.p_wr_req (IF_NAME.p_wr_req),\
// .p_wr_req (IF_NAME.p_wr_req),\
.p_wr_rdy (IF_NAME.p_wr_rdy),\
.rx_error (IF_NAME.rx_error),\
.l2p_clkp (IF_NAME.l2p_clk_p),\
......@@ -250,8 +250,8 @@ endinterface
.l2p_rdy (IF_NAME.l2p_rdy),\
.l_wr_rdy (IF_NAME.l_wr_rdy),\
.p_rd_d_rdy (IF_NAME.p_rd_d_rdy),\
.tx_error (IF_NAME.tx_error),\
.vc_rdy (IF_NAME.vc_rdy)
.tx_error (IF_NAME.tx_error)
// .vc_rdy (IF_NAME.vc_rdy)
`endif // `ifndef __GN4124_BFM_SVH
hdl/spec/testbench/top/main.sv
View file @ f2c83354
......@@ -7,7 +7,8 @@
module main;
reg clk_20m_vcxo = 0;
reg clk_125m_pllref_p = 0;
reg clk_125m_pllref_n = 1;
reg rst_n = 0;
reg adc0_dco = 0;
......@@ -15,7 +16,8 @@ module main;
always #1.25ns adc0_dco <= ~adc0_dco;
always #25ns clk_20m_vcxo <= ~clk_20m_vcxo;
always #4ns clk_125m_pllref_p <= ~clk_125m_pllref_p;
always #4ns clk_125m_pllref_n <= ~clk_125m_pllref_n;
IGN4124PCIMaster I_Gennum ();
......@@ -35,7 +37,8 @@ module main;
.g_simulation("TRUE"),
.g_calib_soft_ip("FALSE")
) DUT (
.clk20_vcxo_i(clk_20m_vcxo),
.clk_125m_pllref_p_i(clk_125m_pllref_p),
.clk_125m_pllref_n_i(clk_125m_pllref_n),
.adc0_dco_p_i(adc0_dco),
.adc0_dco_n_i(~adc0_dco),
.adc0_fr_p_i(adc0_fr),
......@@ -113,7 +116,7 @@ module main;
@(posedge DUT.sys_clk_pll_locked);
#5us;
#15us;
acc.read(0, val);
$display("ID: %x", val);
......@@ -129,6 +132,12 @@ module main;
acc.read('h3304, val); // status
$display("STATUS: %x", val);
#5us;
acc.write('h3600, 'h00000032); // timetag core seconds high
acc.write('h3604, 'h00005a34); // timetag core seconds low
acc.write('h3608, 'h00000000); // timetag core ticks
acc.write('h3300, 'h00000001); // FSM start
#1us;
......@@ -170,6 +179,8 @@ module main;
acc.write('h1000, 'h00000001); // xfer start
acc.read('h3304, val); // status
$display("STATUS: %x", val);
end
......
hdl/spec/testbench/top/wave.do
View file @ f2c83354
......@@ -64,7 +64,9 @@ add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/l
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_stb_t
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt
add wave -noupdate -group Top /main/DUT/clk20_vcxo_i
#add wave -noupdate -group Top /main/DUT/clk20_vcxo_i
add wave -noupdate -group Top /main/DUT/clk_125m_pllref*
add wave -noupdate -group Top /main/DUT/powerup*
add wave -noupdate -group Top /main/DUT/pll25dac_sync_n_o
add wave -noupdate -group Top /main/DUT/pll20dac_sync_n_o
add wave -noupdate -group Top /main/DUT/plldac_din_o
......@@ -72,7 +74,7 @@ add wave -noupdate -group Top /main/DUT/plldac_sclk_o
add wave -noupdate -group Top /main/DUT/led_red_o
add wave -noupdate -group Top /main/DUT/led_green_o
add wave -noupdate -group Top /main/DUT/aux_leds_o
add wave -noupdate -group Top /main/DUT/aux_buttons_i
#add wave -noupdate -group Top /main/DUT/aux_buttons_i
add wave -noupdate -group Top /main/DUT/pcb_ver_i
add wave -noupdate -group Top /main/DUT/carrier_one_wire_b
add wave -noupdate -group Top /main/DUT/L_CLKp
......@@ -152,21 +154,12 @@ add wave -noupdate -group Top /main/DUT/fmc0_sys_scl_b
add wave -noupdate -group Top /main/DUT/fmc0_sys_sda_b
add wave -noupdate -group Top /main/DUT/sys_clk_in
add wave -noupdate -group Top /main/DUT/sys_clk_125_buf
add wave -noupdate -group Top /main/DUT/sys_clk_250_buf
add wave -noupdate -group Top /main/DUT/sys_clk_125
add wave -noupdate -group Top /main/DUT/sys_clk_250
add wave -noupdate -group Top /main/DUT/sys_clk_fb
add wave -noupdate -group Top /main/DUT/sys_clk_pll_locked
add wave -noupdate -group Top /main/DUT/ddr_clk
add wave -noupdate -group Top /main/DUT/ddr_clk_buf
add wave -noupdate -group Top /main/DUT/l_clk
add wave -noupdate -group Top /main/DUT/powerup_reset_cnt
add wave -noupdate -group Top /main/DUT/powerup_rst_n
add wave -noupdate -group Top /main/DUT/sw_rst_fmc0_n
add wave -noupdate -group Top /main/DUT/sw_rst_fmc0_n_o
add wave -noupdate -group Top /main/DUT/sw_rst_fmc0_n_i
add wave -noupdate -group Top /main/DUT/sw_rst_fmc0_n_load
add wave -noupdate -group Top /main/DUT/sys_rst_n
add wave -noupdate -group Top /main/DUT/sw_rst_fmc0
add wave -noupdate -group Top /main/DUT/fmc0_rst_n
add wave -noupdate -group Top /main/DUT/cnx_master_out
add wave -noupdate -group Top /main/DUT/cnx_master_in
......@@ -225,6 +218,7 @@ add wave -noupdate -group Top /main/DUT/led_pwm_val
add wave -noupdate -group Top /main/DUT/led_pwm_val_down
add wave -noupdate -group Top /main/DUT/led_pwm_cnt
add wave -noupdate -group Top /main/DUT/led_pwm
add wave -noupdate -radix hexadecimal -group MEZ /main/DUT/cmp_fmc_adc_mezzanine_0/cnx_*
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sys_clk_i
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sys_rst_n_i
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_adr_i
......@@ -341,6 +335,7 @@ add wave -noupdate -radix unsigned -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/single_shot
add wave -noupdate -radix hexadecimal -group TIMETAG /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_timetag_core/*
add wave -noupdate -group DDRC /main/DUT/cmp_ddr_ctrl/clk_i
add wave -noupdate -group DDRC /main/DUT/cmp_ddr_ctrl/rst_n_i
add wave -noupdate -group DDRC /main/DUT/cmp_ddr_ctrl/status_o
......
hdl/svec/sim/testbench/main.sv
View file @ f2c83354
......@@ -6,12 +6,11 @@
module main;
reg rst_n = 0;
reg clk_20m = 0;
always #25ns clk_20m <= ~clk_20m;
reg clk_125m_pllref_p = 0;
reg clk_125m_pllref_n = 1;
initial begin
repeat(20) @(posedge clk_20m);
repeat(20) @(posedge clk_125m_pllref_p);
rst_n = 1;
end
......@@ -35,6 +34,8 @@ module main;
logic [7:0] adc_frame = 'h0F;
always #1250ps adc0_dco_p <= ~adc0_dco_p;
always #4ns clk_125m_pllref_p <= ~clk_125m_pllref_p;
always #4ns clk_125m_pllref_n <= ~clk_125m_pllref_n;
typedef struct {
rand bit [15:0] data;
......@@ -72,7 +73,8 @@ module main;
)
DUT
(
.clk_20m_vcxo_i(clk_20m),
.clk_125m_pllref_p_i(clk_125m_pllref_p),
.clk_125m_pllref_n_i(clk_125m_pllref_n),
.rst_n_i(rst_n),
.fp_led_line_oen_o(fp_led_line_oen),
......@@ -126,41 +128,39 @@ module main;
init_vme64x_core(acc);
$display("Release FMC0/1 reset\n");
acc.write('h120C, 'h3, A32|SINGLE|D32);
// Enable all interrupts
$display("Enable FMC0 and FMC1 interrupt vectors\n");
acc.write('h1308, 'h3, A32|SINGLE|D32);
acc.read('h1310, d, A32|SINGLE|D32);
$display("VIC interrupt mask = 0x%x\n",d);
acc.write('h1300, 'h3, A32|SINGLE|D32);
$display("Enable TRIGGER and END_ACQ in FMC0/1 EIC\n");
acc.write('h2000, 'h3, A32|SINGLE|D32);
acc.write('h6000, 'h3, A32|SINGLE|D32);
acc.write('h120C, 'h0, A32|SINGLE|D32);
// Trigger setup (sw trigger)
$display("Trigger setup\n");
acc.write('h5308, 'h8, A32|SINGLE|D32);
acc.write('h3308, 'h8, A32|SINGLE|D32);
// Acquisition setup
$display("Acquisition setup\n");
acc.write('h5320, 'h1, A32|SINGLE|D32); // 1 pre-trigger samples
acc.write('h5324, 'hA, A32|SINGLE|D32); // 10 post-trigger samples
acc.write('h5314, 'h1, A32|SINGLE|D32); // 1 shot
acc.write('h3328, 'h1, A32|SINGLE|D32); // 1 pre-trigger samples
acc.write('h332c, 'hA, A32|SINGLE|D32); // 10 post-trigger samples
acc.write('h3314, 'h1, A32|SINGLE|D32); // 1 shot
// Make sure no acquisition is running
acc.write('h5300, 'h2, A32|SINGLE|D32); // Send STOP command
acc.write('h3300, 'h2, A32|SINGLE|D32); // Send STOP command
#2.5us;
acc.write('h1208, 'h10000);
#0.5us;
acc.write('h1208, 'h00000);
#2.0us;
acc.write('h3600, 'h00000032); // timetag core seconds high
acc.write('h3604, 'h00005a34); // timetag core seconds low
acc.write('h3608, 'h00000000); // timetag core ticks
// Start acquisition
$display("Start acquisition\n");
acc.write('h5300, 'h1, A32|SINGLE|D32); // Send START command
acc.write('h3300, 'h1, A32|SINGLE|D32); // Send START command
// Sw trigger
#1us
$display("Software trigger\n");
acc.write('h5310, 'hFF, A32|SINGLE|D32);
acc.write('h3310, 'hFF, A32|SINGLE|D32);
/*
// Data "FIFO" test
......@@ -187,6 +187,7 @@ module main;
end
*/
/* -----\/----- EXCLUDED -----\/-----
acc.write('h2200, 'h0, A32|SINGLE|D32);
for(i=0; i<5; i++)
begin
......@@ -209,6 +210,7 @@ module main;
$display("Read %d: 0x%x\n", i, d);
end
-----/\----- EXCLUDED -----/\----- */
end
......
hdl/svec/sim/testbench/svec.do
View file @ f2c83354
......@@ -5,9 +5,9 @@ set NumericStdNoWarnings 1
#view wave
#view transcript
do wave_interrupt.do
#do wave_interrupt.do
#do wave_ddr.do
#do wave.do
do wave.do
radix -hexadecimal
run 50 us
......
hdl/svec/sim/testbench/wave.do
View file @ f2c83354
......@@ -2,7 +2,7 @@ onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/sys_clk_62_5
add wave -noupdate /main/DUT/sys_clk_125
add wave -noupdate /main/DUT/sys_rst_n
add wave -noupdate /main/DUT/powerup*
add wave -noupdate -divider {wb vme}
add wave -noupdate /main/DUT/cnx_slave_in(0).cyc
add wave -noupdate /main/DUT/cnx_slave_in(0).stb
......@@ -66,6 +66,8 @@ add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_burst_cnt
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/addr_shift
add wave -noupdate /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b/cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/MCB_SYSRST
add wave -noupdate -divider {timetag core}
add wave -noupdate -radix hexadecimal /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_timetag_core/*
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {29753000 ps} 0}
configure wave -namecolwidth 454
......
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