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FMC ADC 100M 14b 4cha - Gateware
Commit ea07b855 authored by mcattin's avatar mcattin
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Commit before making the project hdl-make compliant. 


git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@59 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 8802f990
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hdl/spec/ise_project/_xmsgs/pn_parser.xmsgs
View file @ ea07b855
......@@ -8,7 +8,37 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/carrier_csr.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1574" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;/home/mcattin/projects/wb_spi_master/spi_clgen.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1065" >&quot;<arg fmt="%s" index="1">/home/mcattin/projects/wb_spi_master/spi_clgen.v</arg>&quot; Line <arg fmt="%d" index="2">41</arg>. <arg fmt="%s" index="3">Include file found: &apos;/home/mcattin/projects/wb_spi_master/spi_defines.v&apos; in file &quot;/home/mcattin/projects/wb_spi_master/spi_clgen.v&quot; line 41
</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1065" >&quot;<arg fmt="%s" index="1">/home/mcattin/projects/wb_spi_master/spi_clgen.v</arg>&quot; Line <arg fmt="%d" index="2">42</arg>. <arg fmt="%s" index="3">Include file found: &apos;/home/mcattin/projects/wb_spi_master/timescale.v&apos; in file &quot;/home/mcattin/projects/wb_spi_master/spi_clgen.v&quot; line 42
</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1574" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;/home/mcattin/projects/wb_spi_master/spi_shift.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1065" >&quot;<arg fmt="%s" index="1">/home/mcattin/projects/wb_spi_master/spi_shift.v</arg>&quot; Line <arg fmt="%d" index="2">41</arg>. <arg fmt="%s" index="3">Include file found: &apos;/home/mcattin/projects/wb_spi_master/spi_defines.v&apos; in file &quot;/home/mcattin/projects/wb_spi_master/spi_shift.v&quot; line 41
</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1065" >&quot;<arg fmt="%s" index="1">/home/mcattin/projects/wb_spi_master/spi_shift.v</arg>&quot; Line <arg fmt="%d" index="2">42</arg>. <arg fmt="%s" index="3">Include file found: &apos;/home/mcattin/projects/wb_spi_master/timescale.v&apos; in file &quot;/home/mcattin/projects/wb_spi_master/spi_shift.v&quot; line 42
</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1574" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;/home/mcattin/projects/wb_spi_master/spi_top.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1065" >&quot;<arg fmt="%s" index="1">/home/mcattin/projects/wb_spi_master/spi_top.v</arg>&quot; Line <arg fmt="%d" index="2">42</arg>. <arg fmt="%s" index="3">Include file found: &apos;/home/mcattin/projects/wb_spi_master/spi_defines.v&apos; in file &quot;/home/mcattin/projects/wb_spi_master/spi_top.v&quot; line 42
</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1065" >&quot;<arg fmt="%s" index="1">/home/mcattin/projects/wb_spi_master/spi_top.v</arg>&quot; Line <arg fmt="%d" index="2">43</arg>. <arg fmt="%s" index="3">Include file found: &apos;/home/mcattin/projects/wb_spi_master/timescale.v&apos; in file &quot;/home/mcattin/projects/wb_spi_master/spi_top.v&quot; line 43
</arg>
</msg>
</messages>
......
hdl/spec/ise_project/iseconfig/spec_fmc_adc_100Ms.projectmgr
View file @ ea07b855
......@@ -14,21 +14,25 @@
<ClosedNode>/spec_top - rtl/cmp_fmc_i2c - i2c_master_top - structural</ClosedNode>
<ClosedNode>/spec_top - rtl/cmp_fmc_spi - wb_spi_master</ClosedNode>
<ClosedNode>/spec_top - rtl/cmp_gn4124_core - gn4124_core - rtl</ClosedNode>
<ClosedNode>/spec_top_fmc_adc_100Ms - rtl/cmp_ddr_ctrl - ddr3_ctrl - rtl/cmp_ddr_controller - ddr_controller_bank3_64b - arc</ClosedNode>
<ClosedNode>/spec_top_fmc_adc_100Ms - rtl/cmp_fmc_adc_100Ms_core - fmc_adc_100Ms_core - rtl</ClosedNode>
<ClosedNode>/spec_top_fmc_adc_100Ms - rtl/cmp_fmc_i2c - i2c_master_top - structural</ClosedNode>
<ClosedNode>/spec_top_fmc_adc_100Ms - rtl/cmp_fmc_spi - wb_spi_master</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>spec_top - rtl (/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd)</SelectedItem>
<SelectedItem>cmp_clk_in - serdes_1_to_n_clk_pll_s2_diff - arch_serdes_1_to_n_clk_pll_s2_diff (/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="vertical" >3</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000003c1000000020000000000000000000000000000000064ffffffff000000810000000000000002000003c10000000100000000000000000000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000035c000000020000000000000000000000000000000064ffffffff0000008100000000000000020000035c0000000100000000000000000000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>spec_top - rtl (/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd)</CurrentItem>
<CurrentItem>cmp_clk_in - serdes_1_to_n_clk_pll_s2_diff - arch_serdes_1_to_n_clk_pll_s2_diff (/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
......@@ -38,22 +42,24 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Place &amp; Route</SelectedItem>
<SelectedItem>Add Existing Source</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >2</ScrollbarPosition>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000010e000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010e0000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000415000000010000000100000000000000000000000064ffffffff000000810000000000000001000004150000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Place &amp; Route</CurrentItem>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes/>
<SelectedItems/>
<SelectedItems>
<SelectedItem>gn4124_core_pkg_s6.vhd</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000507000000040101000100000000000000000000000064ffffffff0000008100000000000000040000033c0000000100000000000000d60000000100000000000000840000000100000000000000710000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/ddr_controller_bank3.vhd</CurrentItem>
<CurrentItem>gn4124_core_pkg_s6.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
......@@ -66,7 +72,7 @@
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
<SourceProcessView>000000ff000000000000000200000101000000ec01000000060100000002</SourceProcessView>
<SourceProcessView>000000ff0000000000000002000002050000008001000000060100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
......@@ -105,4 +111,26 @@
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_CDC" guiview="Process" >
<ClosedNodes/>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" />
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Add Existing Source</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000013f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000013f0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
</Project>
hdl/spec/ise_project/spec_fmc_adc_100Ms.gise
View file @ ea07b855
......@@ -136,7 +136,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1301932138" xil_pn:in_ck="6856744517292281709" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1301931810">
<transform xil_pn:end_ts="1302597829" xil_pn:in_ck="6856744517292281709" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1302597523">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -154,84 +154,73 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1301056667" xil_pn:in_ck="2162529744943951648" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4337831395208791850" xil_pn:start_ts="1301056667">
<transform xil_pn:end_ts="1303288526" xil_pn:in_ck="2162529744943951648" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4337831395208791850" xil_pn:start_ts="1303288525">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1301932178" xil_pn:in_ck="3312797925576817273" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1301932138">
<transform xil_pn:end_ts="1304324009" xil_pn:in_ck="3312797925576817273" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1304323974">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.bld"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_ngdbuild.xrpt"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1301933002" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1301932178">
<transform xil_pn:end_ts="1304324766" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1304324009">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.pcf"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_map.map"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_map.mrp"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_map.ncd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_map.ngm"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_map.xrpt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_summary.xml"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_usage.xml"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1301933353" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1301933002">
<transform xil_pn:end_ts="1304325085" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1304324766">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ncd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.pad"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.par"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ptwx"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.unroutes"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.xpi"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_pad.csv"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_pad.txt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_par.xrpt"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1301933441" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1301933353">
<transform xil_pn:end_ts="1304325177" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1304325085">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.bgn"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.bin"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.bit"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.drc"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1300690913" xil_pn:in_ck="1401670161614890390" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="2682241697568822907" xil_pn:start_ts="1300690912">
<transform xil_pn:end_ts="1304342829" xil_pn:in_ck="1401670161614890390" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="2682241697568822907" xil_pn:start_ts="1304342829">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1301043716" xil_pn:in_ck="1401670161614890390" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1301043715">
<transform xil_pn:end_ts="1302701401" xil_pn:in_ck="1401670161614890390" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1302701400">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1301933353" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1301933306">
<transform xil_pn:end_ts="1304325085" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1304325037">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.twr"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.twx"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
</transforms>
......
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