@@ -335,9 +335,24 @@ This block is based on an OpenCores design.
@node Configuration
@chapter Configuration
The @ref{fig:adc_core_fs_clk} is a block diagram of the ADC core part in the sampling clock domain. It contains a ADC data stream de-serialiser, an offset and gain correction (of ADC data)block, an under-sampling block and a trigger unit.
The four channels data and the trigger signal are synchronised to the system clock domain using a FIFO.
The configuration signals coming from registers in the system clock domain are synchronised to the sampling clock within the Wishbone slave (wbgen2 feature).
Optional additional delay on the final trigger (in sampling clock ticks).
The trigger unit is made of a hardware and a software source.
Each hardware and software sources can be enabled independantly.
The two sources are then or'ed together to drive a delay generator.
The delay generator allows to insert an defined number of sampling clock period before the trigger goes to the acquisition state machine.
The hardware trigger source can be either internal (based on an adc input channel) or external (dedicated trigger input).
For both internal and external sources, the polarity can be selected between positive and negative slope (resp. rising and falling edge). By default the polatity is set to positive slope.
For the internal trigger source, the adc input channel and the threshold should be configured.
By default, the channel 1 is selected and the threshold is set to 0.
Note that the threshold is 16-bit signed (two's complement).
The @ref{fig:trig_hw_int} sketches the internal hardware trigger threshold behaviour.
The software trigger source concists in a pulse generated when a write cycle is detected on the "Software trigger".
The @ref{fig:trig_unit} shows the different trigger configurations.
For futher information on the trigger configuration registers @pxref{ADC core registers}.
